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@ -30,9 +30,10 @@ Value RegAlloc::Consume(const IR::Value& value) {
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}
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void RegAlloc::Unref(IR::Inst& inst) {
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inst.DestructiveRemoveUsage();
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if (!inst.HasUses()) {
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Free(inst.Definition<Id>());
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IR::Inst& value_inst{AliasInst(inst)};
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value_inst.DestructiveRemoveUsage();
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if (!value_inst.HasUses()) {
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Free(value_inst.Definition<Id>());
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}
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}
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@ -99,10 +100,7 @@ Value RegAlloc::PeekInst(IR::Inst& inst) {
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}
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Value RegAlloc::ConsumeInst(IR::Inst& inst) {
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inst.DestructiveRemoveUsage();
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if (!inst.HasUses()) {
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Free(inst.Definition<Id>());
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}
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Unref(inst);
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return PeekInst(inst);
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}
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@ -138,4 +136,31 @@ void RegAlloc::Free(Id id) {
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}
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}
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/*static*/ bool RegAlloc::IsAliased(const IR::Inst& inst) {
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switch (inst.GetOpcode()) {
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case IR::Opcode::Identity:
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case IR::Opcode::BitCastU16F16:
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case IR::Opcode::BitCastU32F32:
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case IR::Opcode::BitCastU64F64:
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case IR::Opcode::BitCastF16U16:
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case IR::Opcode::BitCastF32U32:
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case IR::Opcode::BitCastF64U64:
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return true;
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default:
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return false;
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}
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}
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/*static*/ IR::Inst& RegAlloc::AliasInst(IR::Inst& inst) {
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IR::Inst* it{&inst};
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while (IsAliased(*it)) {
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const IR::Value arg{it->Arg(0)};
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if (arg.IsImmediate()) {
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break;
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}
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it = arg.InstRecursive();
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}
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return *it;
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}
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} // namespace Shader::Backend::GLASM
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