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@ -140,6 +140,41 @@ Node ShaderIR::GetSaturatedFloat(Node value, bool saturate) {
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return Operation(OperationCode::FClamp, NO_PRECISE, value, positive_zero, positive_one);
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}
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Node ShaderIR::ConvertIntegerSize(Node value, Tegra::Shader::Register::Size size, bool is_signed) {
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switch (size) {
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case Register::Size::Byte:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE, value,
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Immediate(24));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE, value,
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Immediate(24));
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return value;
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case Register::Size::Short:
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value = SignedOperation(OperationCode::ILogicalShiftLeft, is_signed, NO_PRECISE, value,
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Immediate(16));
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value = SignedOperation(OperationCode::IArithmeticShiftRight, is_signed, NO_PRECISE, value,
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Immediate(16));
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case Register::Size::Word:
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// Default - do nothing
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return value;
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default:
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UNREACHABLE_MSG("Unimplemented conversion size: {}", static_cast<u32>(size));
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}
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}
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Node ShaderIR::GetOperandAbsNegInteger(Node value, bool absolute, bool negate, bool is_signed) {
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if (!is_signed) {
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// Absolute or negate on an unsigned is pointless
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return value;
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}
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if (absolute) {
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value = Operation(OperationCode::IAbsolute, NO_PRECISE, value);
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}
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if (negate) {
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value = Operation(OperationCode::INegate, NO_PRECISE, value);
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}
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return value;
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}
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void ShaderIR::SetRegister(BasicBlock& bb, Register dest, Node src) {
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bb.push_back(Operation(OperationCode::Assign, GetRegister(dest), src));
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}
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