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@ -90,15 +90,10 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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const Node op_b =
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GetConstBufferIndirect(instr.cbuf36.index, instr.cbuf36.offset + 4, index);
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const Node composite =
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Operation(OperationCode::Composite, op_a, op_b, GetRegister(Register::ZeroIndex),
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GetRegister(Register::ZeroIndex));
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MetaComponents meta{{0, 1, 2, 3}};
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bb.push_back(Operation(OperationCode::AssignComposite, meta, composite,
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GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
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GetRegister(Register::ZeroIndex),
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GetRegister(Register::ZeroIndex)));
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SetTemporal(bb, 0, op_a);
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SetTemporal(bb, 1, op_b);
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SetRegister(bb, instr.gpr0, GetTemporal(0));
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SetRegister(bb, instr.gpr0.Value() + 1, GetTemporal(1));
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break;
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}
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default:
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@ -172,10 +167,6 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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break;
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}
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case OpCode::Id::TEX: {
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Tegra::Shader::TextureType texture_type{instr.tex.texture_type};
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const bool is_array = instr.tex.array != 0;
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const bool depth_compare = instr.tex.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex.GetTextureProcessMode();
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UNIMPLEMENTED_IF_MSG(instr.tex.UsesMiscMode(TextureMiscMode::AOFFI),
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"AOFFI is not implemented");
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@ -183,27 +174,12 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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LOG_WARNING(HW_GPU, "TEX.NODEP implementation is incomplete");
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}
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const Node texture = GetTexCode(instr, texture_type, process_mode, depth_compare, is_array);
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MetaComponents meta;
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std::array<Node, 4> dest;
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std::size_t dest_elem = 0;
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for (std::size_t elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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meta.components_map[dest_elem] = static_cast<u32>(elem);
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dest[dest_elem] = GetRegister(instr.gpr0.Value() + dest_elem);
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta), texture, dest[0],
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dest[1], dest[2], dest[3]));
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const TextureType texture_type{instr.tex.texture_type};
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const bool is_array = instr.tex.array != 0;
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const bool depth_compare = instr.tex.UsesMiscMode(TextureMiscMode::DC);
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const auto process_mode = instr.tex.GetTextureProcessMode();
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WriteTexInstructionFloat(
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bb, instr, GetTexCode(instr, texture_type, process_mode, depth_compare, is_array));
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break;
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}
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case OpCode::Id::TEXS: {
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@ -216,13 +192,13 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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LOG_WARNING(HW_GPU, "TEXS.NODEP implementation is incomplete");
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}
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const Node texture =
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const Node4 components =
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GetTexsCode(instr, texture_type, process_mode, depth_compare, is_array);
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if (instr.texs.fp32_flag) {
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WriteTexsInstructionFloat(bb, instr, texture);
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WriteTexsInstructionFloat(bb, instr, components);
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} else {
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WriteTexsInstructionHalfFloat(bb, instr, texture);
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WriteTexsInstructionHalfFloat(bb, instr, components);
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}
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break;
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}
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@ -242,27 +218,8 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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const auto texture_type = instr.tld4.texture_type.Value();
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const bool depth_compare = instr.tld4.UsesMiscMode(TextureMiscMode::DC);
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const bool is_array = instr.tld4.array != 0;
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const Node texture = GetTld4Code(instr, texture_type, depth_compare, is_array);
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MetaComponents meta_components;
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std::array<Node, 4> dest;
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std::size_t dest_elem = 0;
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for (std::size_t elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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meta_components.components_map[dest_elem] = static_cast<u32>(elem);
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dest[dest_elem] = GetRegister(instr.gpr0.Value() + dest_elem);
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++dest_elem;
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}
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std::generate(dest.begin() + dest_elem, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, std::move(meta_components), texture,
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dest[0], dest[1], dest[2], dest[3]));
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WriteTexInstructionFloat(bb, instr,
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GetTld4Code(instr, texture_type, depth_compare, is_array));
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break;
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}
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case OpCode::Id::TLD4S: {
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@ -277,28 +234,34 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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const Node op_a = GetRegister(instr.gpr8);
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const Node op_b = GetRegister(instr.gpr20);
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std::vector<Node> params;
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std::vector<Node> coords;
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// TODO(Subv): Figure out how the sampler type is encoded in the TLD4S instruction.
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if (depth_compare) {
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// Note: TLD4S coordinate encoding works just like TEXS's
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const Node op_y = GetRegister(instr.gpr8.Value() + 1);
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params.push_back(op_a);
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params.push_back(op_y);
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params.push_back(op_b);
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coords.push_back(op_a);
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coords.push_back(op_y);
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coords.push_back(op_b);
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} else {
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params.push_back(op_a);
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params.push_back(op_b);
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coords.push_back(op_a);
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coords.push_back(op_b);
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}
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const auto num_coords = static_cast<u32>(params.size());
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params.push_back(Immediate(static_cast<u32>(instr.tld4s.component)));
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const auto num_coords = static_cast<u32>(coords.size());
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coords.push_back(Immediate(static_cast<u32>(instr.tld4s.component)));
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const auto& sampler =
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GetSampler(instr.sampler, TextureType::Texture2D, false, depth_compare);
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MetaTexture meta{sampler, num_coords};
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WriteTexsInstructionFloat(
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bb, instr, Operation(OperationCode::F4TextureGather, meta, std::move(params)));
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Node4 values;
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for (u32 element = 0; element < values.size(); ++element) {
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auto params = coords;
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MetaTexture meta{sampler, element, num_coords};
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values[element] =
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Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params));
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}
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WriteTexsInstructionFloat(bb, instr, values);
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break;
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}
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case OpCode::Id::TXQ: {
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@ -314,18 +277,15 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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switch (instr.txq.query_type) {
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case Tegra::Shader::TextureQueryType::Dimension: {
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MetaTexture meta_texture{sampler};
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const MetaComponents meta_components{{0, 1, 2, 3}};
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const Node texture = Operation(OperationCode::F4TextureQueryDimensions, meta_texture,
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GetRegister(instr.gpr8));
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std::array<Node, 4> dest;
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for (std::size_t i = 0; i < dest.size(); ++i) {
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dest[i] = GetRegister(instr.gpr0.Value() + i);
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for (u32 element = 0; element < 4; ++element) {
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MetaTexture meta{sampler, element};
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const Node value = Operation(OperationCode::F4TextureQueryDimensions,
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std::move(meta), GetRegister(instr.gpr8));
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SetTemporal(bb, element, value);
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}
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for (u32 i = 0; i < 4; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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}
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bb.push_back(Operation(OperationCode::AssignComposite, meta_components, texture,
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dest[0], dest[1], dest[2], dest[3]));
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break;
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}
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default:
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@ -366,14 +326,17 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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texture_type = TextureType::Texture2D;
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}
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MetaTexture meta_texture{sampler, static_cast<u32>(coords.size())};
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const Node texture =
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Operation(OperationCode::F4TextureQueryLod, meta_texture, std::move(coords));
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for (u32 element = 0; element < 2; ++element) {
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auto params = coords;
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MetaTexture meta_texture{sampler, element, static_cast<u32>(coords.size())};
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const Node value =
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Operation(OperationCode::F4TextureQueryLod, meta_texture, std::move(params));
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SetTemporal(bb, element, value);
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}
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for (u32 element = 0; element < 2; ++element) {
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SetRegister(bb, instr.gpr0.Value() + element, GetTemporal(element));
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}
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const MetaComponents meta_composite{{0, 1, 2, 3}};
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bb.push_back(Operation(OperationCode::AssignComposite, meta_composite, texture,
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GetRegister(instr.gpr0), GetRegister(instr.gpr0.Value() + 1),
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GetRegister(Register::ZeroIndex), GetRegister(Register::ZeroIndex)));
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break;
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}
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case OpCode::Id::TLDS: {
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@ -388,8 +351,7 @@ u32 ShaderIR::DecodeMemory(BasicBlock& bb, u32 pc) {
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LOG_WARNING(HW_GPU, "TMML.NODEP implementation is incomplete");
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}
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const Node texture = GetTldsCode(instr, texture_type, is_array);
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WriteTexsInstructionFloat(bb, instr, texture);
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WriteTexsInstructionFloat(bb, instr, GetTldsCode(instr, texture_type, is_array));
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break;
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}
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default:
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@ -419,57 +381,80 @@ const Sampler& ShaderIR::GetSampler(const Tegra::Shader::Sampler& sampler, Textu
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return *used_samplers.emplace(entry).first;
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}
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void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr, Node texture) {
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void ShaderIR::WriteTexInstructionFloat(BasicBlock& bb, Instruction instr,
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const Node4& components) {
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u32 dest_elem = 0;
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for (u32 elem = 0; elem < 4; ++elem) {
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if (!instr.tex.IsComponentEnabled(elem)) {
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// Skip disabled components
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continue;
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}
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SetTemporal(bb, dest_elem++, components[elem]);
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}
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// After writing values in temporals, move them to the real registers
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for (u32 i = 0; i < dest_elem; ++i) {
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SetRegister(bb, instr.gpr0.Value() + i, GetTemporal(i));
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}
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}
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void ShaderIR::WriteTexsInstructionFloat(BasicBlock& bb, Instruction instr,
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const Node4& components) {
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// TEXS has two destination registers and a swizzle. The first two elements in the swizzle
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// go into gpr0+0 and gpr0+1, and the rest goes into gpr28+0 and gpr28+1
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MetaComponents meta;
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std::array<Node, 4> dest;
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u32 dest_elem = 0;
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for (u32 component = 0; component < 4; ++component) {
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if (!instr.texs.IsComponentEnabled(component)) {
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if (!instr.texs.IsComponentEnabled(component))
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continue;
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}
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meta.components_map[meta.count] = component;
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SetTemporal(bb, dest_elem++, components[component]);
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}
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if (meta.count < 2) {
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for (u32 i = 0; i < dest_elem; ++i) {
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if (i < 2) {
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// Write the first two swizzle components to gpr0 and gpr0+1
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dest[meta.count] = GetRegister(instr.gpr0.Value() + meta.count % 2);
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SetRegister(bb, instr.gpr0.Value() + i % 2, GetTemporal(i));
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} else {
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ASSERT(instr.texs.HasTwoDestinations());
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// Write the rest of the swizzle components to gpr28 and gpr28+1
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dest[meta.count] = GetRegister(instr.gpr28.Value() + meta.count % 2);
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SetRegister(bb, instr.gpr28.Value() + i % 2, GetTemporal(i));
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}
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++meta.count;
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}
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std::generate(dest.begin() + meta.count, dest.end(),
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[&]() { return GetRegister(Register::ZeroIndex); });
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bb.push_back(Operation(OperationCode::AssignComposite, meta, texture, dest[0], dest[1], dest[2],
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dest[3]));
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}
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void ShaderIR::WriteTexsInstructionHalfFloat(BasicBlock& bb, Instruction instr, Node texture) {
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void ShaderIR::WriteTexsInstructionHalfFloat(BasicBlock& bb, Instruction instr,
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const Node4& components) {
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// TEXS.F16 destionation registers are packed in two registers in pairs (just like any half
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// float instruction).
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MetaComponents meta;
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Node4 values;
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u32 dest_elem = 0;
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for (u32 component = 0; component < 4; ++component) {
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if (!instr.texs.IsComponentEnabled(component))
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continue;
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meta.components_map[meta.count++] = component;
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values[dest_elem++] = components[component];
|
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|
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|
}
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if (meta.count == 0)
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|
|
if (dest_elem == 0)
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|
|
return;
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|
bb.push_back(Operation(OperationCode::AssignCompositeHalf, meta, texture,
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|
GetRegister(instr.gpr0), GetRegister(instr.gpr28)));
|
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|
std::generate(values.begin() + dest_elem, values.end(), [&]() { return Immediate(0); });
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|
|
const Node first_value = Operation(OperationCode::HPack2, values[0], values[1]);
|
|
|
|
|
if (dest_elem <= 2) {
|
|
|
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|
SetRegister(bb, instr.gpr0, first_value);
|
|
|
|
|
return;
|
|
|
|
|
}
|
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|
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|
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|
SetTemporal(bb, 0, first_value);
|
|
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|
SetTemporal(bb, 1, Operation(OperationCode::HPack2, values[2], values[3]));
|
|
|
|
|
|
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|
|
SetRegister(bb, instr.gpr0, GetTemporal(0));
|
|
|
|
|
SetRegister(bb, instr.gpr28, GetTemporal(1));
|
|
|
|
|
}
|
|
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|
|
Node ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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|
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|
TextureProcessMode process_mode, bool depth_compare, bool is_array,
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|
|
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|
std::size_t array_offset, std::size_t bias_offset,
|
|
|
|
|
std::vector<Node>&& coords) {
|
|
|
|
|
Node4 ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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|
|
|
|
TextureProcessMode process_mode, bool depth_compare, bool is_array,
|
|
|
|
|
std::size_t array_offset, std::size_t bias_offset,
|
|
|
|
|
std::vector<Node>&& coords) {
|
|
|
|
|
UNIMPLEMENTED_IF_MSG(
|
|
|
|
|
(texture_type == TextureType::Texture3D && (is_array || depth_compare)) ||
|
|
|
|
|
(texture_type == TextureType::TextureCube && is_array && depth_compare),
|
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|
|
@ -495,24 +480,31 @@ Node ShaderIR::GetTextureCode(Instruction instr, TextureType texture_type,
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|
std::optional<u32> array_offset_value;
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|
|
if (is_array)
|
|
|
|
|
array_offset_value = static_cast<u32>(array_offset);
|
|
|
|
|
MetaTexture meta{sampler, static_cast<u32>(coords.size()), array_offset_value};
|
|
|
|
|
std::vector<Node> params = std::move(coords);
|
|
|
|
|
|
|
|
|
|
const auto coords_count = static_cast<u32>(coords.size());
|
|
|
|
|
|
|
|
|
|
if (process_mode != TextureProcessMode::None && gl_lod_supported) {
|
|
|
|
|
if (process_mode == TextureProcessMode::LZ) {
|
|
|
|
|
params.push_back(Immediate(0.0f));
|
|
|
|
|
coords.push_back(Immediate(0.0f));
|
|
|
|
|
} else {
|
|
|
|
|
// If present, lod or bias are always stored in the register indexed by the gpr20 field
|
|
|
|
|
// with an offset depending on the usage of the other registers
|
|
|
|
|
params.push_back(GetRegister(instr.gpr20.Value() + bias_offset));
|
|
|
|
|
// If present, lod or bias are always stored in the register indexed by the gpr20
|
|
|
|
|
// field with an offset depending on the usage of the other registers
|
|
|
|
|
coords.push_back(GetRegister(instr.gpr20.Value() + bias_offset));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return Operation(read_method, meta, std::move(params));
|
|
|
|
|
Node4 values;
|
|
|
|
|
for (u32 element = 0; element < values.size(); ++element) {
|
|
|
|
|
auto params = coords;
|
|
|
|
|
MetaTexture meta{sampler, element, coords_count, array_offset_value};
|
|
|
|
|
values[element] = Operation(read_method, std::move(meta), std::move(params));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return values;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Node ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
|
|
|
|
TextureProcessMode process_mode, bool depth_compare, bool is_array) {
|
|
|
|
|
Node4 ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
|
|
|
|
TextureProcessMode process_mode, bool depth_compare, bool is_array) {
|
|
|
|
|
const bool lod_bias_enabled =
|
|
|
|
|
(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ);
|
|
|
|
|
|
|
|
|
@ -551,8 +543,8 @@ Node ShaderIR::GetTexCode(Instruction instr, TextureType texture_type,
|
|
|
|
|
0, std::move(coords));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Node ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
|
|
|
|
TextureProcessMode process_mode, bool depth_compare, bool is_array) {
|
|
|
|
|
Node4 ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
|
|
|
|
TextureProcessMode process_mode, bool depth_compare, bool is_array) {
|
|
|
|
|
const bool lod_bias_enabled =
|
|
|
|
|
(process_mode != TextureProcessMode::None && process_mode != TextureProcessMode::LZ);
|
|
|
|
|
|
|
|
|
@ -593,8 +585,8 @@ Node ShaderIR::GetTexsCode(Instruction instr, TextureType texture_type,
|
|
|
|
|
(coord_count > 2 ? 1 : 0), std::move(coords));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Node ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
|
|
|
|
|
bool is_array) {
|
|
|
|
|
Node4 ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool depth_compare,
|
|
|
|
|
bool is_array) {
|
|
|
|
|
const std::size_t coord_count = GetCoordCount(texture_type);
|
|
|
|
|
const std::size_t total_coord_count = coord_count + (is_array ? 1 : 0);
|
|
|
|
|
const std::size_t total_reg_count = total_coord_count + (depth_compare ? 1 : 0);
|
|
|
|
@ -604,24 +596,31 @@ Node ShaderIR::GetTld4Code(Instruction instr, TextureType texture_type, bool dep
|
|
|
|
|
// First coordinate index is the gpr8 or gpr8 + 1 when arrays are used
|
|
|
|
|
const u64 coord_register = array_register + (is_array ? 1 : 0);
|
|
|
|
|
|
|
|
|
|
std::vector<Node> params;
|
|
|
|
|
std::vector<Node> coords;
|
|
|
|
|
|
|
|
|
|
for (size_t i = 0; i < coord_count; ++i) {
|
|
|
|
|
params.push_back(GetRegister(coord_register + i));
|
|
|
|
|
coords.push_back(GetRegister(coord_register + i));
|
|
|
|
|
}
|
|
|
|
|
std::optional<u32> array_offset;
|
|
|
|
|
if (is_array) {
|
|
|
|
|
array_offset = static_cast<u32>(params.size());
|
|
|
|
|
params.push_back(GetRegister(array_register));
|
|
|
|
|
array_offset = static_cast<u32>(coords.size());
|
|
|
|
|
coords.push_back(GetRegister(array_register));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, depth_compare);
|
|
|
|
|
MetaTexture meta{sampler, static_cast<u32>(params.size()), array_offset};
|
|
|
|
|
|
|
|
|
|
return Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params));
|
|
|
|
|
Node4 values;
|
|
|
|
|
for (u32 element = 0; element < values.size(); ++element) {
|
|
|
|
|
auto params = coords;
|
|
|
|
|
MetaTexture meta{sampler, element, static_cast<u32>(coords.size()), array_offset};
|
|
|
|
|
values[element] =
|
|
|
|
|
Operation(OperationCode::F4TextureGather, std::move(meta), std::move(params));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return values;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
Node ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is_array) {
|
|
|
|
|
Node4 ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is_array) {
|
|
|
|
|
const std::size_t type_coord_count = GetCoordCount(texture_type);
|
|
|
|
|
const std::size_t total_coord_count = type_coord_count + (is_array ? 1 : 0);
|
|
|
|
|
const bool lod_enabled = instr.tlds.GetTextureProcessMode() == TextureProcessMode::LL;
|
|
|
|
@ -636,36 +635,41 @@ Node ShaderIR::GetTldsCode(Instruction instr, TextureType texture_type, bool is_
|
|
|
|
|
? static_cast<u64>(instr.gpr20.Value())
|
|
|
|
|
: coord_register + 1;
|
|
|
|
|
|
|
|
|
|
std::vector<Node> params;
|
|
|
|
|
std::vector<Node> coords;
|
|
|
|
|
|
|
|
|
|
for (std::size_t i = 0; i < type_coord_count; ++i) {
|
|
|
|
|
const bool last = (i == (type_coord_count - 1)) && (type_coord_count > 1);
|
|
|
|
|
params.push_back(GetRegister(last ? last_coord_register : coord_register + i));
|
|
|
|
|
coords.push_back(GetRegister(last ? last_coord_register : coord_register + i));
|
|
|
|
|
}
|
|
|
|
|
std::optional<u32> array_offset;
|
|
|
|
|
if (is_array) {
|
|
|
|
|
array_offset = static_cast<u32>(params.size());
|
|
|
|
|
params.push_back(GetRegister(array_register));
|
|
|
|
|
array_offset = static_cast<u32>(coords.size());
|
|
|
|
|
coords.push_back(GetRegister(array_register));
|
|
|
|
|
}
|
|
|
|
|
const auto coords_count = static_cast<u32>(params.size());
|
|
|
|
|
const auto coords_count = static_cast<u32>(coords.size());
|
|
|
|
|
|
|
|
|
|
if (lod_enabled) {
|
|
|
|
|
// When lod is used always is in grp20
|
|
|
|
|
params.push_back(GetRegister(instr.gpr20));
|
|
|
|
|
coords.push_back(GetRegister(instr.gpr20));
|
|
|
|
|
} else {
|
|
|
|
|
params.push_back(Immediate(0));
|
|
|
|
|
coords.push_back(Immediate(0));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
const auto& sampler = GetSampler(instr.sampler, texture_type, is_array, false);
|
|
|
|
|
MetaTexture meta{sampler, coords_count, array_offset};
|
|
|
|
|
|
|
|
|
|
return Operation(OperationCode::F4TexelFetch, std::move(meta), std::move(params));
|
|
|
|
|
Node4 values;
|
|
|
|
|
for (u32 element = 0; element < values.size(); ++element) {
|
|
|
|
|
auto params = coords;
|
|
|
|
|
MetaTexture meta{sampler, element, coords_count, array_offset};
|
|
|
|
|
values[element] =
|
|
|
|
|
Operation(OperationCode::F4TexelFetch, std::move(meta), std::move(params));
|
|
|
|
|
}
|
|
|
|
|
return values;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
std::tuple<std::size_t, std::size_t> ShaderIR::ValidateAndGetCoordinateElement(
|
|
|
|
|
TextureType texture_type, bool depth_compare, bool is_array, bool lod_bias_enabled,
|
|
|
|
|
std::size_t max_coords, std::size_t max_inputs) {
|
|
|
|
|
|
|
|
|
|
const std::size_t coord_count = GetCoordCount(texture_type);
|
|
|
|
|
|
|
|
|
|
std::size_t total_coord_count = coord_count + (is_array ? 1 : 0) + (depth_compare ? 1 : 0);
|
|
|
|
|