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vfp: Move FPSID, FPEXC, and FPSCR values over to enums.

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Also got rid of duplicate definitions of some of these values.
pull/8/head
Lioncash 10 years ago
parent 1576a318f2
commit 3e576219c4
3 changed files with 104 additions and 150 deletions
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141
src/core/arm/skyeye_common/vfp/asm_vfp.h
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@ -7,80 +7,77 @@
#pragma once
#define FPSID cr0
#define FPSCR cr1
#define MVFR1 cr6
#define MVFR0 cr7
#define FPEXC cr8
#define FPINST cr9
#define FPINST2 cr10
// FPSID Information
// Note that these are used as values and not as flags.
enum : u32 {
VFP_FPSID_IMPLMEN = 0, // Implementation code. Should be the same as cp15 0 c0 0
VFP_FPSID_SW = 0, // Software emulation bit value
VFP_FPSID_SUBARCH = 0x2, // Subarchitecture version number
VFP_FPSID_PARTNUM = 0x1, // Part number
VFP_FPSID_VARIANT = 0x1, // Variant number
VFP_FPSID_REVISION = 0x1 // Revision number
};
/* FPSID bits */
#define FPSID_IMPLEMENTER_BIT (24)
#define FPSID_IMPLEMENTER_MASK (0xff << FPSID_IMPLEMENTER_BIT)
#define FPSID_SOFTWARE (1<<23)
#define FPSID_FORMAT_BIT (21)
#define FPSID_FORMAT_MASK (0x3 << FPSID_FORMAT_BIT)
#define FPSID_NODOUBLE (1<<20)
#define FPSID_ARCH_BIT (16)
#define FPSID_ARCH_MASK (0xF << FPSID_ARCH_BIT)
#define FPSID_PART_BIT (8)
#define FPSID_PART_MASK (0xFF << FPSID_PART_BIT)
#define FPSID_VARIANT_BIT (4)
#define FPSID_VARIANT_MASK (0xF << FPSID_VARIANT_BIT)
#define FPSID_REV_BIT (0)
#define FPSID_REV_MASK (0xF << FPSID_REV_BIT)
// FPEXC bits
enum : u32 {
FPEXC_EX = (1U << 31U),
FPEXC_EN = (1 << 30),
FPEXC_DEX = (1 << 29),
FPEXC_FP2V = (1 << 28),
FPEXC_VV = (1 << 27),
FPEXC_TFV = (1 << 26),
FPEXC_LENGTH_BIT = (8),
FPEXC_LENGTH_MASK = (7 << FPEXC_LENGTH_BIT),
FPEXC_IDF = (1 << 7),
FPEXC_IXF = (1 << 4),
FPEXC_UFF = (1 << 3),
FPEXC_OFF = (1 << 2),
FPEXC_DZF = (1 << 1),
FPEXC_IOF = (1 << 0),
FPEXC_TRAP_MASK = (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
};
/* FPEXC bits */
#define FPEXC_EX (1 << 31)
#define FPEXC_EN (1 << 30)
#define FPEXC_DEX (1 << 29)
#define FPEXC_FP2V (1 << 28)
#define FPEXC_VV (1 << 27)
#define FPEXC_TFV (1 << 26)
#define FPEXC_LENGTH_BIT (8)
#define FPEXC_LENGTH_MASK (7 << FPEXC_LENGTH_BIT)
#define FPEXC_IDF (1 << 7)
#define FPEXC_IXF (1 << 4)
#define FPEXC_UFF (1 << 3)
#define FPEXC_OFF (1 << 2)
#define FPEXC_DZF (1 << 1)
#define FPEXC_IOF (1 << 0)
#define FPEXC_TRAP_MASK (FPEXC_IDF|FPEXC_IXF|FPEXC_UFF|FPEXC_OFF|FPEXC_DZF|FPEXC_IOF)
// FPSCR Flags
enum : u32 {
FPSCR_NFLAG = (1U << 31U), // Negative condition flag
FPSCR_ZFLAG = (1 << 30), // Zero condition flag
FPSCR_CFLAG = (1 << 29), // Carry condition flag
FPSCR_VFLAG = (1 << 28), // Overflow condition flag
/* FPSCR bits */
#define FPSCR_DEFAULT_NAN (1<<25)
#define FPSCR_FLUSHTOZERO (1<<24)
#define FPSCR_ROUND_NEAREST (0<<22)
#define FPSCR_ROUND_PLUSINF (1<<22)
#define FPSCR_ROUND_MINUSINF (2<<22)
#define FPSCR_ROUND_TOZERO (3<<22)
#define FPSCR_RMODE_BIT (22)
#define FPSCR_RMODE_MASK (3 << FPSCR_RMODE_BIT)
#define FPSCR_STRIDE_BIT (20)
#define FPSCR_STRIDE_MASK (3 << FPSCR_STRIDE_BIT)
#define FPSCR_LENGTH_BIT (16)
#define FPSCR_LENGTH_MASK (7 << FPSCR_LENGTH_BIT)
#define FPSCR_IOE (1<<8)
#define FPSCR_DZE (1<<9)
#define FPSCR_OFE (1<<10)
#define FPSCR_UFE (1<<11)
#define FPSCR_IXE (1<<12)
#define FPSCR_IDE (1<<15)
#define FPSCR_IOC (1<<0)
#define FPSCR_DZC (1<<1)
#define FPSCR_OFC (1<<2)
#define FPSCR_UFC (1<<3)
#define FPSCR_IXC (1<<4)
#define FPSCR_IDC (1<<7)
FPSCR_QC = (1 << 27), // Cumulative saturation bit
FPSCR_AHP = (1 << 26), // Alternative half-precision control bit
FPSCR_DEFAULT_NAN = (1 << 25), // Default NaN mode control bit
FPSCR_FLUSH_TO_ZERO = (1 << 24), // Flush-to-zero mode control bit
FPSCR_RMODE_MASK = (3 << 22), // Rounding Mode bit mask
FPSCR_STRIDE_MASK = (3 << 20), // Vector stride bit mask
FPSCR_LENGTH_MASK = (7 << 16), // Vector length bit mask
/* MVFR0 bits */
#define MVFR0_A_SIMD_BIT (0)
#define MVFR0_A_SIMD_MASK (0xf << MVFR0_A_SIMD_BIT)
FPSCR_IDE = (1 << 15), // Input Denormal exception trap enable.
FPSCR_IXE = (1 << 12), // Inexact exception trap enable
FPSCR_UFE = (1 << 11), // Undeflow exception trap enable
FPSCR_OFE = (1 << 10), // Overflow exception trap enable
FPSCR_DZE = (1 << 9), // Division by Zero exception trap enable
FPSCR_IOE = (1 << 8), // Invalid Operation exception trap enable
/* Bit patterns for decoding the packaged operation descriptors */
#define VFPOPDESC_LENGTH_BIT (9)
#define VFPOPDESC_LENGTH_MASK (0x07 << VFPOPDESC_LENGTH_BIT)
#define VFPOPDESC_UNUSED_BIT (24)
#define VFPOPDESC_UNUSED_MASK (0xFF << VFPOPDESC_UNUSED_BIT)
#define VFPOPDESC_OPDESC_MASK (~(VFPOPDESC_LENGTH_MASK | VFPOPDESC_UNUSED_MASK))
FPSCR_IDC = (1 << 7), // Input Denormal cumulative exception bit
FPSCR_IXC = (1 << 4), // Inexact cumulative exception bit
FPSCR_UFC = (1 << 3), // Undeflow cumulative exception bit
FPSCR_OFC = (1 << 2), // Overflow cumulative exception bit
FPSCR_DZC = (1 << 1), // Division by Zero cumulative exception bit
FPSCR_IOC = (1 << 0), // Invalid Operation cumulative exception bit
};
// FPSCR bit offsets
enum : u32 {
FPSCR_RMODE_BIT = 22,
FPSCR_STRIDE_BIT = 20,
FPSCR_LENGTH_BIT = 16,
};
// FPSCR rounding modes
enum : u32 {
FPSCR_ROUND_NEAREST = (0 << 22),
FPSCR_ROUND_PLUSINF = (1 << 22),
FPSCR_ROUND_MINUSINF = (2 << 22),
FPSCR_ROUND_TOZERO = (3 << 22)
};

1
src/core/arm/skyeye_common/vfp/vfp.cpp
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@ -23,6 +23,7 @@
#include "common/common.h"
#include "core/arm/skyeye_common/armdefs.h"
#include "core/arm/skyeye_common/vfp/asm_vfp.h"
#include "core/arm/skyeye_common/vfp/vfp.h"
//ARMul_State* persistent_state; /* function calls from SoftFloat lib don't have an access to ARMul_state. */

68
src/core/arm/skyeye_common/vfp/vfp.h
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@ -36,75 +36,31 @@ unsigned VFPSTC (ARMul_State * state, unsigned type, ARMword instr, ARMword * va
unsigned VFPLDC(ARMul_State* state, unsigned type, ARMword instr, ARMword value);
unsigned VFPCDP(ARMul_State* state, unsigned type, ARMword instr);
/* FPSID Information */
#define VFP_FPSID_IMPLMEN 0 /* should be the same as cp15 0 c0 0*/
#define VFP_FPSID_SW 0
#define VFP_FPSID_SUBARCH 0x2 /* VFP version. Current is v3 (not strict) */
#define VFP_FPSID_PARTNUM 0x1
#define VFP_FPSID_VARIANT 0x1
#define VFP_FPSID_REVISION 0x1
/* FPEXC Flags */
#define VFP_FPEXC_EX 1<<31
#define VFP_FPEXC_EN 1<<30
/* FPSCR Flags */
#define VFP_FPSCR_NFLAG 1<<31
#define VFP_FPSCR_ZFLAG 1<<30
#define VFP_FPSCR_CFLAG 1<<29
#define VFP_FPSCR_VFLAG 1<<28
#define VFP_FPSCR_AHP 1<<26 /* Alternative Half Precision */
#define VFP_FPSCR_DN 1<<25 /* Default NaN */
#define VFP_FPSCR_FZ 1<<24 /* Flush-to-zero */
#define VFP_FPSCR_RMODE 3<<22 /* Rounding Mode */
#define VFP_FPSCR_STRIDE 3<<20 /* Stride (vector) */
#define VFP_FPSCR_LEN 7<<16 /* Stride (vector) */
#define VFP_FPSCR_IDE 1<<15 /* Input Denormal exc */
#define VFP_FPSCR_IXE 1<<12 /* Inexact exc */
#define VFP_FPSCR_UFE 1<<11 /* Undeflow exc */
#define VFP_FPSCR_OFE 1<<10 /* Overflow exc */
#define VFP_FPSCR_DZE 1<<9 /* Division by Zero exc */
#define VFP_FPSCR_IOE 1<<8 /* Invalid Operation exc */
#define VFP_FPSCR_IDC 1<<7 /* Input Denormal cum exc */
#define VFP_FPSCR_IXC 1<<4 /* Inexact cum exc */
#define VFP_FPSCR_UFC 1<<3 /* Undeflow cum exc */
#define VFP_FPSCR_OFC 1<<2 /* Overflow cum exc */
#define VFP_FPSCR_DZC 1<<1 /* Division by Zero cum exc */
#define VFP_FPSCR_IOC 1<<0 /* Invalid Operation cum exc */
/* Inline instructions. Note: Used in a cpp file as well */
#ifdef __cplusplus
extern "C" {
#endif
int32_t vfp_get_float(ARMul_State * state, unsigned int reg);
void vfp_put_float(ARMul_State * state, int32_t val, unsigned int reg);
uint64_t vfp_get_double(ARMul_State * state, unsigned int reg);
void vfp_put_double(ARMul_State * state, uint64_t val, unsigned int reg);
void vfp_raise_exceptions(ARMul_State * state, uint32_t exceptions, uint32_t inst, uint32_t fpscr);
s32 vfp_get_float(ARMul_State* state, u32 reg);
void vfp_put_float(ARMul_State* state, s32 val, u32 reg);
u64 vfp_get_double(ARMul_State* state, u32 reg);
void vfp_put_double(ARMul_State* state, u64 val, u32 reg);
void vfp_raise_exceptions(ARMul_State* state, u32 exceptions, u32 inst, u32 fpscr);
u32 vfp_single_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
u32 vfp_double_cpdo(ARMul_State* state, u32 inst, u32 fpscr);
/* MRC */
// MRC
void VMRS(ARMul_State* state, ARMword reg, ARMword Rt, ARMword* value);
void VMOVBRS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword n, ARMword* value);
void VMOVBRRD(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
void VMOVBRRSS(ARMul_State* state, ARMword to_arm, ARMword t, ARMword t2, ARMword n, ARMword* value1, ARMword* value2);
void VMOVI(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
void VMOVR(ARMul_State* state, ARMword single, ARMword d, ARMword imm);
/* MCR */
// MCR
void VMSR(ARMul_State* state, ARMword reg, ARMword Rt);
/* STC */
// STC
int VSTM(ARMul_State* state, int type, ARMword instr, ARMword* value);
int VPUSH(ARMul_State* state, int type, ARMword instr, ARMword* value);
int VSTR(ARMul_State* state, int type, ARMword instr, ARMword* value);
/* LDC */
// LDC
int VLDM(ARMul_State* state, int type, ARMword instr, ARMword value);
int VPOP(ARMul_State* state, int type, ARMword instr, ARMword value);
int VLDR(ARMul_State* state, int type, ARMword instr, ARMword value);
#ifdef __cplusplus
}
#endif

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