mirror of https://github.com/yuzu-mirror/yuzu
shader: Partial implementation of LDC
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ab46371247
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Mode : u64 {
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Default,
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IL,
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IS,
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ISL,
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};
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enum class Size : u64 {
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U8,
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S8,
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U16,
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S16,
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B32,
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B64,
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};
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std::pair<IR::U32, IR::U32> Slot(IR::IREmitter& ir, Mode mode, const IR::U32& imm_index,
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const IR::U32& reg, const IR::U32& imm) {
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switch (mode) {
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case Mode::Default:
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return {imm_index, ir.IAdd(reg, imm)};
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default:
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break;
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}
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throw NotImplementedException("Mode {}", mode);
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}
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} // Anonymous namespace
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void TranslatorVisitor::LDC(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<20, 16, s64> offset;
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BitField<36, 5, u64> index;
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BitField<44, 2, Mode> mode;
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BitField<48, 3, Size> size;
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} const ldc{insn};
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const IR::U32 imm_index{ir.Imm32(static_cast<u32>(ldc.index))};
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const IR::U32 reg{X(ldc.src_reg)};
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const IR::U32 imm{ir.Imm32(static_cast<s32>(ldc.offset))};
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const auto [index, offset]{Slot(ir, ldc.mode, imm_index, reg, imm)};
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switch (ldc.size) {
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case Size::U8:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, false));
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break;
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case Size::S8:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 8, true));
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break;
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case Size::U16:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, false));
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break;
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case Size::S16:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 16, true));
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break;
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case Size::B32:
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X(ldc.dest_reg, ir.GetCbuf(index, offset, 32, false));
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break;
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case Size::B64: {
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if (!IR::IsAligned(ldc.dest_reg, 2)) {
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throw NotImplementedException("Unaligned destination register");
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}
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const IR::Value vector{ir.UnpackUint2x32(ir.GetCbuf(index, offset, 64, false))};
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for (int i = 0; i < 2; ++i) {
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X(ldc.dest_reg + i, IR::U32{ir.CompositeExtract(vector, i)});
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}
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break;
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}
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default:
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throw NotImplementedException("Invalid size {}", ldc.size.Value());
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}
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}
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} // namespace Shader::Maxwell
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