mirror of https://github.com/yuzu-mirror/yuzu
shader: Initial support for textures and TEX
ReinUsesLisp
4 years ago
committed by
ameerj
parent
7d6ba5b984
commit
ab46371247
@ -0,0 +1,146 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <boost/container/static_vector.hpp>
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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class ImageOperands {
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public:
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explicit ImageOperands(EmitContext& ctx, bool has_bias, bool has_lod, bool has_lod_clamp,
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Id lod, Id offset) {
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if (has_bias) {
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const Id bias{has_lod_clamp ? ctx.OpCompositeExtract(ctx.F32[1], lod, 0) : lod};
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Add(spv::ImageOperandsMask::Bias, bias);
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}
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if (has_lod) {
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const Id lod_value{has_lod_clamp ? ctx.OpCompositeExtract(ctx.F32[1], lod, 0) : lod};
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Add(spv::ImageOperandsMask::Lod, lod_value);
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}
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if (Sirit::ValidId(offset)) {
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Add(spv::ImageOperandsMask::Offset, offset);
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}
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if (has_lod_clamp) {
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const Id lod_clamp{has_bias ? ctx.OpCompositeExtract(ctx.F32[1], lod, 1) : lod};
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Add(spv::ImageOperandsMask::MinLod, lod_clamp);
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}
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}
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void Add(spv::ImageOperandsMask new_mask, Id value) {
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mask = static_cast<spv::ImageOperandsMask>(static_cast<unsigned>(mask) |
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static_cast<unsigned>(new_mask));
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operands.push_back(value);
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}
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std::span<const Id> Span() const noexcept {
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return std::span{operands.data(), operands.size()};
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}
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spv::ImageOperandsMask Mask() const noexcept {
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return mask;
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}
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private:
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boost::container::static_vector<Id, 3> operands;
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spv::ImageOperandsMask mask{};
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};
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Id Texture(EmitContext& ctx, const IR::Value& index) {
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if (index.IsImmediate()) {
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const TextureDefinition def{ctx.textures.at(index.U32())};
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return ctx.OpLoad(def.type, def.id);
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}
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throw NotImplementedException("Indirect texture sample");
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}
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template <typename MethodPtrType, typename... Args>
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Id Emit(MethodPtrType sparse_ptr, MethodPtrType non_sparse_ptr, EmitContext& ctx, IR::Inst* inst,
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Id result_type, Args&&... args) {
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IR::Inst* const sparse{inst->GetAssociatedPseudoOperation(IR::Opcode::GetSparseFromOp)};
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if (!sparse) {
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return (ctx.*non_sparse_ptr)(result_type, std::forward<Args>(args)...);
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}
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const Id struct_type{ctx.TypeStruct(ctx.U32[1], result_type)};
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const Id sample{(ctx.*sparse_ptr)(struct_type, std::forward<Args>(args)...)};
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const Id resident_code{ctx.OpCompositeExtract(ctx.U32[1], sample, 0U)};
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sparse->SetDefinition(ctx.OpImageSparseTexelsResident(ctx.U1, resident_code));
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sparse->Invalidate();
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return ctx.OpCompositeExtract(result_type, sample, 1U);
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}
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} // Anonymous namespace
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Id EmitBindlessImageSampleImplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitBindlessImageSampleExplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitBindlessImageSampleDrefImplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitBindlessImageSampleDrefExplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitBoundImageSampleImplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitBoundImageSampleExplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitBoundImageSampleDrefImplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitBoundImageSampleDrefExplicitLod(EmitContext&) {
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throw LogicError("Unreachable instruction");
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}
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Id EmitImageSampleImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
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Id bias_lc, Id offset) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0, bias_lc,
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offset);
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return Emit(&EmitContext::OpImageSparseSampleImplicitLod,
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&EmitContext::OpImageSampleImplicitLod, ctx, inst, ctx.F32[4], Texture(ctx, index),
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coords, operands.Mask(), operands.Span());
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}
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Id EmitImageSampleExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index, Id coords,
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Id lod_lc, Id offset) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, false, true, info.has_lod_clamp != 0, lod_lc, offset);
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return Emit(&EmitContext::OpImageSparseSampleExplicitLod,
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&EmitContext::OpImageSampleExplicitLod, ctx, inst, ctx.F32[4], Texture(ctx, index),
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coords, operands.Mask(), operands.Span());
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}
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Id EmitImageSampleDrefImplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
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Id coords, Id dref, Id bias_lc, Id offset) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, info.has_bias != 0, false, info.has_lod_clamp != 0, bias_lc,
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offset);
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return Emit(&EmitContext::OpImageSparseSampleDrefImplicitLod,
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&EmitContext::OpImageSampleDrefImplicitLod, ctx, inst, ctx.F32[1],
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Texture(ctx, index), coords, dref, operands.Mask(), operands.Span());
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}
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Id EmitImageSampleDrefExplicitLod(EmitContext& ctx, IR::Inst* inst, const IR::Value& index,
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Id coords, Id dref, Id lod_lc, Id offset) {
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const auto info{inst->Flags<IR::TextureInstInfo>()};
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const ImageOperands operands(ctx, false, true, info.has_lod_clamp != 0, lod_lc, offset);
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return Emit(&EmitContext::OpImageSparseSampleDrefExplicitLod,
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&EmitContext::OpImageSampleDrefExplicitLod, ctx, inst, ctx.F32[1],
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Texture(ctx, index), coords, dref, operands.Mask(), operands.Span());
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}
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} // namespace Shader::Backend::SPIRV
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@ -0,0 +1,232 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <optional>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/ir/modifiers.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Blod : u64 {
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None,
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LZ,
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LB,
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LL,
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INVALIDBLOD4,
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INVALIDBLOD5,
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LBA,
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LLA,
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};
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enum class TextureType : u64 {
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_1D,
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ARRAY_1D,
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_2D,
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ARRAY_2D,
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_3D,
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ARRAY_3D,
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CUBE,
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ARRAY_CUBE,
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};
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Shader::TextureType GetType(TextureType type, bool dc) {
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switch (type) {
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case TextureType::_1D:
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return dc ? Shader::TextureType::Shadow1D : Shader::TextureType::Color1D;
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case TextureType::ARRAY_1D:
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return dc ? Shader::TextureType::ShadowArray1D : Shader::TextureType::ColorArray1D;
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case TextureType::_2D:
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return dc ? Shader::TextureType::Shadow2D : Shader::TextureType::Color2D;
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case TextureType::ARRAY_2D:
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return dc ? Shader::TextureType::ShadowArray2D : Shader::TextureType::ColorArray2D;
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case TextureType::_3D:
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return dc ? Shader::TextureType::Shadow3D : Shader::TextureType::Color3D;
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case TextureType::ARRAY_3D:
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throw NotImplementedException("3D array texture type");
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case TextureType::CUBE:
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return dc ? Shader::TextureType::ShadowCube : Shader::TextureType::ColorCube;
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case TextureType::ARRAY_CUBE:
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return dc ? Shader::TextureType::ShadowArrayCube : Shader::TextureType::ColorArrayCube;
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}
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throw NotImplementedException("Invalid texture type {}", type);
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}
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IR::Value MakeCoords(TranslatorVisitor& v, IR::Reg reg, TextureType type) {
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const auto read_array{[&]() -> IR::F32 { return v.ir.ConvertUToF(32, v.X(reg)); }};
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switch (type) {
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case TextureType::_1D:
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return v.F(reg);
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case TextureType::ARRAY_1D:
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return v.ir.CompositeConstruct(read_array(), v.F(reg + 1));
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case TextureType::_2D:
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return v.ir.CompositeConstruct(v.F(reg), v.F(reg + 1));
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case TextureType::ARRAY_2D:
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return v.ir.CompositeConstruct(read_array(), v.F(reg + 1), v.F(reg + 2));
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case TextureType::_3D:
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return v.ir.CompositeConstruct(v.F(reg), v.F(reg + 1), v.F(reg + 2));
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case TextureType::ARRAY_3D:
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throw NotImplementedException("3D array texture type");
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case TextureType::CUBE:
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return v.ir.CompositeConstruct(v.F(reg), v.F(reg + 1), v.F(reg + 2));
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case TextureType::ARRAY_CUBE:
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return v.ir.CompositeConstruct(read_array(), v.F(reg + 1), v.F(reg + 2), v.F(reg + 3));
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}
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throw NotImplementedException("Invalid texture type {}", type);
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}
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IR::F32 MakeLod(TranslatorVisitor& v, IR::Reg& reg, Blod blod) {
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switch (blod) {
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case Blod::None:
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return v.ir.Imm32(0.0f);
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case Blod::LZ:
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return v.ir.Imm32(0.0f);
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case Blod::LB:
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case Blod::LL:
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case Blod::LBA:
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case Blod::LLA:
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return v.F(reg++);
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case Blod::INVALIDBLOD4:
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case Blod::INVALIDBLOD5:
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break;
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}
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throw NotImplementedException("Invalid blod {}", blod);
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}
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IR::Value MakeOffset(TranslatorVisitor& v, IR::Reg& reg, TextureType type) {
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const IR::U32 value{v.X(reg++)};
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switch (type) {
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case TextureType::_1D:
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case TextureType::ARRAY_1D:
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return v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(4));
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case TextureType::_2D:
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case TextureType::ARRAY_2D:
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return v.ir.CompositeConstruct(v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(4)),
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v.ir.BitFieldExtract(value, v.ir.Imm32(4), v.ir.Imm32(4)));
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case TextureType::_3D:
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case TextureType::ARRAY_3D:
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return v.ir.CompositeConstruct(v.ir.BitFieldExtract(value, v.ir.Imm32(0), v.ir.Imm32(4)),
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v.ir.BitFieldExtract(value, v.ir.Imm32(4), v.ir.Imm32(4)),
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v.ir.BitFieldExtract(value, v.ir.Imm32(8), v.ir.Imm32(4)));
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case TextureType::CUBE:
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case TextureType::ARRAY_CUBE:
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throw NotImplementedException("Illegal offset on CUBE sample");
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}
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throw NotImplementedException("Invalid texture type {}", type);
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}
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bool HasExplicitLod(Blod blod) {
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switch (blod) {
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case Blod::LL:
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case Blod::LLA:
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case Blod::LZ:
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return true;
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default:
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return false;
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}
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}
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void Impl(TranslatorVisitor& v, u64 insn, bool aoffi, Blod blod, bool lc,
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std::optional<u32> cbuf_offset) {
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union {
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u64 raw;
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BitField<35, 1, u64> ndv;
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BitField<49, 1, u64> nodep;
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BitField<50, 1, u64> dc;
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BitField<51, 3, IR::Pred> sparse_pred;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> coord_reg;
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BitField<20, 8, IR::Reg> meta_reg;
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BitField<28, 3, TextureType> type;
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BitField<31, 4, u64> mask;
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} const tex{insn};
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if (lc) {
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throw NotImplementedException("LC");
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}
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const IR::Value coords{MakeCoords(v, tex.coord_reg, tex.type)};
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IR::Reg meta_reg{tex.meta_reg};
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IR::Value handle;
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IR::Value offset;
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IR::F32 dref;
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IR::F32 lod_clamp;
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if (cbuf_offset) {
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handle = v.ir.Imm32(*cbuf_offset);
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} else {
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handle = v.X(meta_reg++);
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}
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const IR::F32 lod{MakeLod(v, meta_reg, blod)};
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if (aoffi) {
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offset = MakeOffset(v, meta_reg, tex.type);
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}
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if (tex.dc != 0) {
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dref = v.F(meta_reg++);
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}
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IR::TextureInstInfo info{};
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info.type.Assign(GetType(tex.type, tex.dc != 0));
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info.has_bias.Assign(blod == Blod::LB || blod == Blod::LBA ? 1 : 0);
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info.has_lod_clamp.Assign(lc ? 1 : 0);
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const IR::Value sample{[&]() -> IR::Value {
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if (tex.dc == 0) {
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if (HasExplicitLod(blod)) {
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return v.ir.ImageSampleExplicitLod(handle, coords, lod, offset, lod_clamp, info);
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} else {
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return v.ir.ImageSampleImplicitLod(handle, coords, lod, offset, lod_clamp, info);
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}
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}
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if (HasExplicitLod(blod)) {
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return v.ir.ImageSampleDrefExplicitLod(handle, coords, dref, lod, offset, lod_clamp,
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info);
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} else {
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return v.ir.ImageSampleDrefImplicitLod(handle, coords, dref, lod, offset, lod_clamp,
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info);
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}
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}()};
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for (int element = 0; element < 4; ++element) {
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if (((tex.mask >> element) & 1) == 0) {
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continue;
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}
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IR::F32 value;
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if (tex.dc != 0) {
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value = element < 3 ? IR::F32{sample} : v.ir.Imm32(1.0f);
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} else {
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value = IR::F32{v.ir.CompositeExtract(sample, element)};
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}
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v.F(tex.dest_reg + element, value);
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}
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if (tex.sparse_pred != IR::Pred::PT) {
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v.ir.SetPred(tex.sparse_pred, v.ir.LogicalNot(v.ir.GetSparseFromOp(sample)));
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}
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}
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} // Anonymous namespace
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void TranslatorVisitor::TEX(u64 insn) {
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union {
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u64 raw;
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BitField<54, 1, u64> aoffi;
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BitField<55, 3, Blod> blod;
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BitField<58, 1, u64> lc;
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BitField<36, 13, u64> cbuf_offset;
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} const tex{insn};
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Impl(*this, insn, tex.aoffi != 0, tex.blod, tex.lc != 0, static_cast<u32>(tex.cbuf_offset));
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}
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void TranslatorVisitor::TEX_b(u64 insn) {
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union {
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u64 raw;
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BitField<36, 1, u64> aoffi;
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BitField<37, 3, Blod> blod;
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BitField<40, 1, u64> lc;
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} const tex{insn};
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Impl(*this, insn, tex.aoffi != 0, tex.blod, tex.lc != 0, std::nullopt);
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}
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} // namespace Shader::Maxwell
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@ -0,0 +1,199 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <optional>
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#include <boost/container/flat_set.hpp>
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#include <boost/container/small_vector.hpp>
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#include "shader_recompiler/environment.h"
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#include "shader_recompiler/frontend/ir/basic_block.h"
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#include "shader_recompiler/frontend/ir/ir_emitter.h"
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#include "shader_recompiler/ir_opt/passes.h"
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#include "shader_recompiler/shader_info.h"
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namespace Shader::Optimization {
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namespace {
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struct ConstBufferAddr {
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u32 index;
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u32 offset;
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};
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struct TextureInst {
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ConstBufferAddr cbuf;
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IR::Inst* inst;
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IR::Block* block;
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};
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using TextureInstVector = boost::container::small_vector<TextureInst, 24>;
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using VisitedBlocks = boost::container::flat_set<IR::Block*, std::less<IR::Block*>,
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boost::container::small_vector<IR::Block*, 2>>;
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IR::Opcode IndexedInstruction(const IR::Inst& inst) {
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switch (inst.Opcode()) {
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case IR::Opcode::BindlessImageSampleImplicitLod:
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case IR::Opcode::BoundImageSampleImplicitLod:
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return IR::Opcode::ImageSampleImplicitLod;
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case IR::Opcode::BoundImageSampleExplicitLod:
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||||
case IR::Opcode::BindlessImageSampleExplicitLod:
|
||||
return IR::Opcode::ImageSampleExplicitLod;
|
||||
case IR::Opcode::BoundImageSampleDrefImplicitLod:
|
||||
case IR::Opcode::BindlessImageSampleDrefImplicitLod:
|
||||
return IR::Opcode::ImageSampleDrefImplicitLod;
|
||||
case IR::Opcode::BoundImageSampleDrefExplicitLod:
|
||||
case IR::Opcode::BindlessImageSampleDrefExplicitLod:
|
||||
return IR::Opcode::ImageSampleDrefExplicitLod;
|
||||
default:
|
||||
return IR::Opcode::Void;
|
||||
}
|
||||
}
|
||||
|
||||
bool IsBindless(const IR::Inst& inst) {
|
||||
switch (inst.Opcode()) {
|
||||
case IR::Opcode::BindlessImageSampleImplicitLod:
|
||||
case IR::Opcode::BindlessImageSampleExplicitLod:
|
||||
case IR::Opcode::BindlessImageSampleDrefImplicitLod:
|
||||
case IR::Opcode::BindlessImageSampleDrefExplicitLod:
|
||||
return true;
|
||||
case IR::Opcode::BoundImageSampleImplicitLod:
|
||||
case IR::Opcode::BoundImageSampleExplicitLod:
|
||||
case IR::Opcode::BoundImageSampleDrefImplicitLod:
|
||||
case IR::Opcode::BoundImageSampleDrefExplicitLod:
|
||||
return false;
|
||||
default:
|
||||
throw InvalidArgument("Invalid opcode {}", inst.Opcode());
|
||||
}
|
||||
}
|
||||
|
||||
bool IsTextureInstruction(const IR::Inst& inst) {
|
||||
return IndexedInstruction(inst) != IR::Opcode::Void;
|
||||
}
|
||||
|
||||
std::optional<ConstBufferAddr> Track(IR::Block* block, const IR::Value& value,
|
||||
VisitedBlocks& visited) {
|
||||
if (value.IsImmediate()) {
|
||||
// Immediates can't be a storage buffer
|
||||
return std::nullopt;
|
||||
}
|
||||
const IR::Inst* const inst{value.InstRecursive()};
|
||||
if (inst->Opcode() == IR::Opcode::GetCbuf) {
|
||||
const IR::Value index{inst->Arg(0)};
|
||||
const IR::Value offset{inst->Arg(1)};
|
||||
if (!index.IsImmediate()) {
|
||||
// Reading a bindless texture from variable indices is valid
|
||||
// but not supported here at the moment
|
||||
return std::nullopt;
|
||||
}
|
||||
if (!offset.IsImmediate()) {
|
||||
// TODO: Support arrays of textures
|
||||
return std::nullopt;
|
||||
}
|
||||
return ConstBufferAddr{
|
||||
.index{index.U32()},
|
||||
.offset{offset.U32()},
|
||||
};
|
||||
}
|
||||
// Reversed loops are more likely to find the right result
|
||||
for (size_t arg = inst->NumArgs(); arg--;) {
|
||||
IR::Block* inst_block{block};
|
||||
if (inst->Opcode() == IR::Opcode::Phi) {
|
||||
// If we are going through a phi node, mark the current block as visited
|
||||
visited.insert(block);
|
||||
// and skip already visited blocks to avoid looping forever
|
||||
IR::Block* const phi_block{inst->PhiBlock(arg)};
|
||||
if (visited.contains(phi_block)) {
|
||||
// Already visited, skip
|
||||
continue;
|
||||
}
|
||||
inst_block = phi_block;
|
||||
}
|
||||
const std::optional storage_buffer{Track(inst_block, inst->Arg(arg), visited)};
|
||||
if (storage_buffer) {
|
||||
return *storage_buffer;
|
||||
}
|
||||
}
|
||||
return std::nullopt;
|
||||
}
|
||||
|
||||
TextureInst MakeInst(Environment& env, IR::Block* block, IR::Inst& inst) {
|
||||
ConstBufferAddr addr;
|
||||
if (IsBindless(inst)) {
|
||||
VisitedBlocks visited;
|
||||
const std::optional<ConstBufferAddr> track_addr{Track(block, IR::Value{&inst}, visited)};
|
||||
if (!track_addr) {
|
||||
throw NotImplementedException("Failed to track bindless texture constant buffer");
|
||||
}
|
||||
addr = *track_addr;
|
||||
} else {
|
||||
addr = ConstBufferAddr{
|
||||
.index{env.TextureBoundBuffer()},
|
||||
.offset{inst.Arg(0).U32()},
|
||||
};
|
||||
}
|
||||
return TextureInst{
|
||||
.cbuf{addr},
|
||||
.inst{&inst},
|
||||
.block{block},
|
||||
};
|
||||
}
|
||||
|
||||
class Descriptors {
|
||||
public:
|
||||
explicit Descriptors(TextureDescriptors& descriptors_) : descriptors{descriptors_} {}
|
||||
|
||||
u32 Add(const TextureDescriptor& descriptor) {
|
||||
// TODO: Handle arrays
|
||||
auto it{std::ranges::find_if(descriptors, [&descriptor](const TextureDescriptor& existing) {
|
||||
return descriptor.cbuf_index == existing.cbuf_index &&
|
||||
descriptor.cbuf_offset == existing.cbuf_offset &&
|
||||
descriptor.type == existing.type;
|
||||
})};
|
||||
if (it != descriptors.end()) {
|
||||
return static_cast<u32>(std::distance(descriptors.begin(), it));
|
||||
}
|
||||
descriptors.push_back(descriptor);
|
||||
return static_cast<u32>(descriptors.size()) - 1;
|
||||
}
|
||||
|
||||
private:
|
||||
TextureDescriptors& descriptors;
|
||||
};
|
||||
} // Anonymous namespace
|
||||
|
||||
void TexturePass(Environment& env, IR::Program& program) {
|
||||
TextureInstVector to_replace;
|
||||
for (IR::Function& function : program.functions) {
|
||||
for (IR::Block* const block : function.post_order_blocks) {
|
||||
for (IR::Inst& inst : block->Instructions()) {
|
||||
if (!IsTextureInstruction(inst)) {
|
||||
continue;
|
||||
}
|
||||
to_replace.push_back(MakeInst(env, block, inst));
|
||||
}
|
||||
}
|
||||
}
|
||||
// Sort instructions to visit textures by constant buffer index, then by offset
|
||||
std::ranges::sort(to_replace, [](const auto& lhs, const auto& rhs) {
|
||||
return lhs.cbuf.offset < rhs.cbuf.offset;
|
||||
});
|
||||
std::stable_sort(to_replace.begin(), to_replace.end(), [](const auto& lhs, const auto& rhs) {
|
||||
return lhs.cbuf.index < rhs.cbuf.index;
|
||||
});
|
||||
Descriptors descriptors{program.info.texture_descriptors};
|
||||
for (TextureInst& texture_inst : to_replace) {
|
||||
// TODO: Handle arrays
|
||||
IR::Inst* const inst{texture_inst.inst};
|
||||
const u32 index{descriptors.Add(TextureDescriptor{
|
||||
.type{inst->Flags<IR::TextureInstInfo>().type},
|
||||
.cbuf_index{texture_inst.cbuf.index},
|
||||
.cbuf_offset{texture_inst.cbuf.offset},
|
||||
.count{1},
|
||||
})};
|
||||
inst->ReplaceOpcode(IndexedInstruction(*inst));
|
||||
inst->SetArg(0, IR::Value{index});
|
||||
}
|
||||
}
|
||||
|
||||
} // namespace Shader::Optimization
|
||||
Loading…
Reference in New Issue