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					@ -25,6 +25,7 @@ void Timers::Reset()
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					  for (CounterState& cs : m_states)
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					  for (CounterState& cs : m_states)
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					  {
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					  {
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					    cs.mode.bits = 0;
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					    cs.mode.bits = 0;
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					    cs.mode.interrupt_request_n = true;
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					    cs.counter = 0;
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					    cs.counter = 0;
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					    cs.target = 0;
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					    cs.target = 0;
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					    cs.gate = false;
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					    cs.gate = false;
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					@ -231,13 +232,13 @@ void Timers::WriteRegister(u32 offset, u32 value)
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					    case 0x04:
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					    case 0x04:
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					    {
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					    {
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					      static constexpr u32 WRITE_MASK = 0b1110001111111111;
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					      Log_DebugPrintf("Timer %u write mode register 0x%04X", timer_index, value);
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					      Log_DebugPrintf("Timer %u write mode register 0x%04X", timer_index, value);
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					      cs.mode.bits = value & u32(0x1FFF);
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					      cs.mode.bits = (value & WRITE_MASK) | (cs.mode.bits & ~WRITE_MASK);
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					      cs.use_external_clock = (cs.mode.clock_source & (timer_index == 2 ? 2 : 1)) != 0;
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					      cs.use_external_clock = (cs.mode.clock_source & (timer_index == 2 ? 2 : 1)) != 0;
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					      cs.counter = 0;
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					      cs.counter = 0;
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					      cs.irq_done = false;
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					      cs.irq_done = false;
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					      if (cs.mode.irq_pulse_n)
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					        cs.mode.interrupt_request_n = true;
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					      UpdateCountingEnabled(cs);
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					      UpdateCountingEnabled(cs);
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					      UpdateIRQ(timer_index);
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					      UpdateIRQ(timer_index);
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