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@ -235,7 +235,14 @@ u32 GPU::ReadRegister(u32 offset)
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return ReadGPUREAD();
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return ReadGPUREAD();
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case 0x04:
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case 0x04:
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{
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// code can be dependent on the odd/even bit, so update the GPU state when reading.
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// we can mitigate this slightly by only updating when the raster is actually hitting a new line
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if (IsRasterScanlinePending())
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m_tick_event->InvokeEarly(true);
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return m_GPUSTAT.bits;
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return m_GPUSTAT.bits;
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}
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default:
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default:
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Log_ErrorPrintf("Unhandled register read: %02X", offset);
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Log_ErrorPrintf("Unhandled register read: %02X", offset);
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@ -455,6 +462,11 @@ void GPU::UpdateSliceTicks()
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m_tick_event->SetPeriod(GPUTicksToSystemTicks(ticks_until_hblank));
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m_tick_event->SetPeriod(GPUTicksToSystemTicks(ticks_until_hblank));
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}
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}
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bool GPU::IsRasterScanlinePending() const
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{
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return (GetPendingGPUTicks() + m_crtc_state.current_tick_in_scanline) >= m_crtc_state.horizontal_total;
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}
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void GPU::Execute(TickCount ticks)
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void GPU::Execute(TickCount ticks)
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{
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{
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// convert cpu/master clock to GPU ticks, accounting for partial cycles because of the non-integer divider
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// convert cpu/master clock to GPU ticks, accounting for partial cycles because of the non-integer divider
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