mirror of https://github.com/yuzu-mirror/yuzu
shader: Implement LDS, STS, LDL, and STS and use SPIR-V 1.4 when available
ReinUsesLisp
4 years ago
committed by
ameerj
parent
84298ce191
commit
e860870dd2
@ -0,0 +1,175 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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Id Pointer(EmitContext& ctx, Id pointer_type, Id array, Id offset, u32 shift) {
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const Id shift_id{ctx.Constant(ctx.U32[1], shift)};
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const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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return ctx.OpAccessChain(pointer_type, array, ctx.u32_zero_value, index);
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}
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Id Word(EmitContext& ctx, Id offset) {
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const Id shift_id{ctx.Constant(ctx.U32[1], 2U)};
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const Id index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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const Id pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index)};
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return ctx.OpLoad(ctx.U32[1], pointer);
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}
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std::pair<Id, Id> ExtractArgs(EmitContext& ctx, Id offset, u32 mask, u32 count) {
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const Id shift{ctx.OpShiftLeftLogical(ctx.U32[1], offset, ctx.Constant(ctx.U32[1], 3U))};
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const Id bit{ctx.OpBitwiseAnd(ctx.U32[1], shift, ctx.Constant(ctx.U32[1], mask))};
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const Id count_id{ctx.Constant(ctx.U32[1], count)};
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return {bit, count_id};
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}
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} // Anonymous namespace
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Id EmitLoadSharedU8(EmitContext& ctx, Id offset) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{
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ctx.OpAccessChain(ctx.shared_u8, ctx.shared_memory_u8, ctx.u32_zero_value, offset)};
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return ctx.OpUConvert(ctx.U32[1], ctx.OpLoad(ctx.U8, pointer));
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} else {
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const auto [bit, count]{ExtractArgs(ctx, offset, 24, 8)};
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return ctx.OpBitFieldUExtract(ctx.U32[1], Word(ctx, offset), bit, count);
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}
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}
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Id EmitLoadSharedS8(EmitContext& ctx, Id offset) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{
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ctx.OpAccessChain(ctx.shared_u8, ctx.shared_memory_u8, ctx.u32_zero_value, offset)};
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return ctx.OpSConvert(ctx.U32[1], ctx.OpLoad(ctx.U8, pointer));
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} else {
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const auto [bit, count]{ExtractArgs(ctx, offset, 24, 8)};
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return ctx.OpBitFieldSExtract(ctx.U32[1], Word(ctx, offset), bit, count);
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}
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}
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Id EmitLoadSharedU16(EmitContext& ctx, Id offset) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u16, ctx.shared_memory_u16, offset, 1)};
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return ctx.OpUConvert(ctx.U32[1], ctx.OpLoad(ctx.U16, pointer));
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} else {
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const auto [bit, count]{ExtractArgs(ctx, offset, 16, 16)};
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return ctx.OpBitFieldUExtract(ctx.U32[1], Word(ctx, offset), bit, count);
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}
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}
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Id EmitLoadSharedS16(EmitContext& ctx, Id offset) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u16, ctx.shared_memory_u16, offset, 1)};
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return ctx.OpSConvert(ctx.U32[1], ctx.OpLoad(ctx.U16, pointer));
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} else {
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const auto [bit, count]{ExtractArgs(ctx, offset, 16, 16)};
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return ctx.OpBitFieldSExtract(ctx.U32[1], Word(ctx, offset), bit, count);
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}
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}
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Id EmitLoadSharedU32(EmitContext& ctx, Id offset) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u32, ctx.shared_memory_u32, offset, 2)};
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return ctx.OpLoad(ctx.U32[1], pointer);
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} else {
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return Word(ctx, offset);
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}
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}
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Id EmitLoadSharedU64(EmitContext& ctx, Id offset) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u32x2, ctx.shared_memory_u32x2, offset, 3)};
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return ctx.OpLoad(ctx.U32[2], pointer);
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} else {
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const Id shift_id{ctx.Constant(ctx.U32[1], 2U)};
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const Id base_index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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const Id next_index{ctx.OpIAdd(ctx.U32[1], base_index, ctx.Constant(ctx.U32[1], 1U))};
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const Id lhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, base_index)};
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const Id rhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, next_index)};
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return ctx.OpCompositeConstruct(ctx.U32[2], ctx.OpLoad(ctx.U32[1], lhs_pointer),
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ctx.OpLoad(ctx.U32[1], rhs_pointer));
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}
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}
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Id EmitLoadSharedU128(EmitContext& ctx, Id offset) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u32x4, ctx.shared_memory_u32x4, offset, 4)};
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return ctx.OpLoad(ctx.U32[4], pointer);
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}
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const Id shift_id{ctx.Constant(ctx.U32[1], 2U)};
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const Id base_index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift_id)};
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std::array<Id, 4> values{};
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for (u32 i = 0; i < 4; ++i) {
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const Id index{i == 0 ? base_index
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: ctx.OpIAdd(ctx.U32[1], base_index, ctx.Constant(ctx.U32[1], i))};
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const Id pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index)};
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values[i] = ctx.OpLoad(ctx.U32[1], pointer);
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}
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return ctx.OpCompositeConstruct(ctx.U32[4], values);
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}
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void EmitWriteSharedU8(EmitContext& ctx, Id offset, Id value) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{
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ctx.OpAccessChain(ctx.shared_u8, ctx.shared_memory_u8, ctx.u32_zero_value, offset)};
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ctx.OpStore(pointer, ctx.OpUConvert(ctx.U8, value));
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} else {
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ctx.OpFunctionCall(ctx.void_id, ctx.shared_store_u8_func, offset, value);
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}
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}
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void EmitWriteSharedU16(EmitContext& ctx, Id offset, Id value) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u16, ctx.shared_memory_u16, offset, 1)};
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ctx.OpStore(pointer, ctx.OpUConvert(ctx.U16, value));
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} else {
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ctx.OpFunctionCall(ctx.void_id, ctx.shared_store_u16_func, offset, value);
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}
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}
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void EmitWriteSharedU32(EmitContext& ctx, Id offset, Id value) {
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Id pointer{};
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if (ctx.profile.support_explicit_workgroup_layout) {
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pointer = Pointer(ctx, ctx.shared_u32, ctx.shared_memory_u32, offset, 2);
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} else {
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const Id shift{ctx.Constant(ctx.U32[1], 2U)};
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const Id word_offset{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift)};
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pointer = ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, word_offset);
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}
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ctx.OpStore(pointer, value);
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}
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void EmitWriteSharedU64(EmitContext& ctx, Id offset, Id value) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u32x2, ctx.shared_memory_u32x2, offset, 3)};
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ctx.OpStore(pointer, value);
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return;
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}
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const Id shift{ctx.Constant(ctx.U32[1], 2U)};
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const Id word_offset{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift)};
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const Id next_offset{ctx.OpIAdd(ctx.U32[1], word_offset, ctx.Constant(ctx.U32[1], 1U))};
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const Id lhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, word_offset)};
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const Id rhs_pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, next_offset)};
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ctx.OpStore(lhs_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 0U));
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ctx.OpStore(rhs_pointer, ctx.OpCompositeExtract(ctx.U32[1], value, 1U));
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}
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void EmitWriteSharedU128(EmitContext& ctx, Id offset, Id value) {
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if (ctx.profile.support_explicit_workgroup_layout) {
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const Id pointer{Pointer(ctx, ctx.shared_u32x4, ctx.shared_memory_u32x4, offset, 4)};
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ctx.OpStore(pointer, value);
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return;
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}
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const Id shift{ctx.Constant(ctx.U32[1], 2U)};
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const Id base_index{ctx.OpShiftRightArithmetic(ctx.U32[1], offset, shift)};
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for (u32 i = 0; i < 4; ++i) {
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const Id index{i == 0 ? base_index
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: ctx.OpIAdd(ctx.U32[1], base_index, ctx.Constant(ctx.U32[1], i))};
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const Id pointer{ctx.OpAccessChain(ctx.shared_u32, ctx.shared_memory_u32, index)};
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ctx.OpStore(pointer, ctx.OpCompositeExtract(ctx.U32[1], value, i));
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}
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}
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} // namespace Shader::Backend::SPIRV
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@ -0,0 +1,197 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class Size : u64 {
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U8,
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S8,
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U16,
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S16,
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B32,
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B64,
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B128,
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};
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IR::U32 Offset(TranslatorVisitor& v, u64 insn) {
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union {
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u64 raw;
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BitField<8, 8, IR::Reg> offset_reg;
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BitField<20, 24, u64> absolute_offset;
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BitField<20, 24, s64> relative_offset;
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} const encoding{insn};
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if (encoding.offset_reg == IR::Reg::RZ) {
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return v.ir.Imm32(static_cast<u32>(encoding.absolute_offset));
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} else {
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const s32 relative{static_cast<s32>(encoding.relative_offset.Value())};
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return v.ir.IAdd(v.X(encoding.offset_reg), v.ir.Imm32(relative));
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}
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}
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std::pair<int, bool> GetSize(u64 insn) {
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union {
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u64 raw;
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BitField<48, 3, Size> size;
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} const encoding{insn};
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const Size nnn = encoding.size;
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switch (encoding.size) {
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case Size::U8:
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return {8, false};
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case Size::S8:
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return {8, true};
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case Size::U16:
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return {16, false};
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case Size::S16:
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return {16, true};
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case Size::B32:
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return {32, false};
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case Size::B64:
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return {64, false};
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case Size::B128:
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return {128, false};
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default:
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throw NotImplementedException("Invalid size {}", encoding.size.Value());
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}
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}
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IR::Reg Reg(u64 insn) {
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union {
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u64 raw;
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BitField<0, 8, IR::Reg> reg;
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} const encoding{insn};
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return encoding.reg;
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}
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IR::U32 ByteOffset(IR::IREmitter& ir, const IR::U32& offset) {
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return ir.BitwiseAnd(ir.ShiftLeftLogical(offset, ir.Imm32(3)), ir.Imm32(24));
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}
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IR::U32 ShortOffset(IR::IREmitter& ir, const IR::U32& offset) {
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return ir.BitwiseAnd(ir.ShiftLeftLogical(offset, ir.Imm32(3)), ir.Imm32(16));
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}
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} // Anonymous namespace
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void TranslatorVisitor::LDL(u64 insn) {
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const IR::U32 offset{Offset(*this, insn)};
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const IR::U32 word_offset{ir.ShiftRightArithmetic(offset, ir.Imm32(2))};
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const IR::Reg dest{Reg(insn)};
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const auto [bit_size, is_signed]{GetSize(insn)};
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switch (bit_size) {
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case 8: {
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const IR::U32 bit{ByteOffset(ir, offset)};
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X(dest, ir.BitFieldExtract(ir.LoadLocal(word_offset), bit, ir.Imm32(8), is_signed));
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break;
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}
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case 16: {
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const IR::U32 bit{ShortOffset(ir, offset)};
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X(dest, ir.BitFieldExtract(ir.LoadLocal(word_offset), bit, ir.Imm32(16), is_signed));
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break;
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}
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case 32:
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case 64:
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case 128:
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if (!IR::IsAligned(dest, bit_size / 32)) {
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throw NotImplementedException("Unaligned destination register {}", dest);
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}
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X(dest, ir.LoadLocal(word_offset));
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for (int i = 1; i < bit_size / 32; ++i) {
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X(dest + i, ir.LoadLocal(ir.IAdd(word_offset, ir.Imm32(i))));
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}
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break;
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}
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}
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void TranslatorVisitor::LDS(u64 insn) {
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const IR::U32 offset{Offset(*this, insn)};
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const IR::Reg dest{Reg(insn)};
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const auto [bit_size, is_signed]{GetSize(insn)};
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const IR::Value value{ir.LoadShared(bit_size, is_signed, offset)};
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switch (bit_size) {
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case 8:
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case 16:
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case 32:
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X(dest, IR::U32{value});
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break;
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case 64:
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case 128:
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if (!IR::IsAligned(dest, bit_size / 32)) {
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throw NotImplementedException("Unaligned destination register {}", dest);
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}
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for (int element = 0; element < bit_size / 32; ++element) {
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X(dest + element, IR::U32{ir.CompositeExtract(value, element)});
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}
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break;
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}
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}
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void TranslatorVisitor::STL(u64 insn) {
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const IR::U32 offset{Offset(*this, insn)};
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const IR::U32 word_offset{ir.ShiftRightArithmetic(offset, ir.Imm32(2))};
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const IR::Reg reg{Reg(insn)};
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const IR::U32 src{X(reg)};
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const int bit_size{GetSize(insn).first};
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switch (bit_size) {
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case 8: {
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const IR::U32 bit{ByteOffset(ir, offset)};
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const IR::U32 value{ir.BitFieldInsert(ir.LoadLocal(word_offset), src, bit, ir.Imm32(8))};
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ir.WriteLocal(word_offset, value);
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break;
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}
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case 16: {
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const IR::U32 bit{ShortOffset(ir, offset)};
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const IR::U32 value{ir.BitFieldInsert(ir.LoadLocal(word_offset), src, bit, ir.Imm32(16))};
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ir.WriteLocal(word_offset, value);
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break;
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}
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case 32:
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case 64:
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case 128:
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if (!IR::IsAligned(reg, bit_size / 32)) {
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throw NotImplementedException("Unaligned source register");
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}
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ir.WriteLocal(word_offset, src);
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for (int i = 1; i < bit_size / 32; ++i) {
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ir.WriteLocal(ir.IAdd(word_offset, ir.Imm32(i)), X(reg + i));
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}
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break;
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}
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}
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void TranslatorVisitor::STS(u64 insn) {
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const IR::U32 offset{Offset(*this, insn)};
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const IR::Reg reg{Reg(insn)};
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const int bit_size{GetSize(insn).first};
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switch (bit_size) {
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case 8:
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case 16:
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case 32:
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ir.WriteShared(bit_size, offset, X(reg));
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break;
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case 64:
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if (!IR::IsAligned(reg, 2)) {
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throw NotImplementedException("Unaligned source register {}", reg);
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}
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ir.WriteShared(64, offset, ir.CompositeConstruct(X(reg), X(reg + 1)));
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break;
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case 128: {
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if (!IR::IsAligned(reg, 2)) {
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throw NotImplementedException("Unaligned source register {}", reg);
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}
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const IR::Value vector{ir.CompositeConstruct(X(reg), X(reg + 1), X(reg + 2), X(reg + 3))};
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ir.WriteShared(128, offset, vector);
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break;
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}
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}
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}
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} // namespace Shader::Maxwell
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