mirror of https://github.com/yuzu-mirror/yuzu
shader: Implement DMNMX, DSET, DSETP
ameerj
4 years ago
parent
56be556eee
commit
e4e1cc11b8
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void DSET(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a_reg;
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BitField<39, 3, IR::Pred> pred;
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BitField<42, 1, u64> neg_pred;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_b;
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BitField<45, 2, BooleanOp> bop;
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BitField<48, 4, FPCompareOp> compare_op;
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BitField<52, 1, u64> bf;
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BitField<53, 1, u64> negate_b;
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BitField<54, 1, u64> abs_a;
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} const dset{insn};
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const IR::F64 op_a{v.ir.FPAbsNeg(v.D(dset.src_a_reg), dset.abs_a != 0, dset.negate_a != 0)};
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const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dset.abs_b != 0, dset.negate_b != 0)};
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IR::U1 pred{v.ir.GetPred(dset.pred)};
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if (dset.neg_pred != 0) {
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pred = v.ir.LogicalNot(pred);
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}
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const IR::U1 cmp_result{FloatingPointCompare(v.ir, op_a, op_b, dset.compare_op)};
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const IR::U1 bop_result{PredicateCombine(v.ir, cmp_result, pred, dset.bop)};
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const IR::U32 one_mask{v.ir.Imm32(-1)};
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const IR::U32 fp_one{v.ir.Imm32(0x3f800000)};
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const IR::U32 fail_result{v.ir.Imm32(0)};
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const IR::U32 pass_result{dset.bf == 0 ? one_mask : fp_one};
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v.X(dset.dest_reg, IR::U32{v.ir.Select(bop_result, pass_result, fail_result)});
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}
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} // Anonymous namespace
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void TranslatorVisitor::DSET_reg(u64 insn) {
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DSET(*this, insn, GetDoubleReg20(insn));
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}
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void TranslatorVisitor::DSET_cbuf(u64 insn) {
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DSET(*this, insn, GetDoubleCbuf(insn));
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}
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void TranslatorVisitor::DSET_imm(u64 insn) {
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DSET(*this, insn, GetDoubleImm20(insn));
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}
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} // namespace Shader::Maxwell
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void DMNMX(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_a_reg;
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BitField<39, 3, IR::Pred> pred;
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BitField<42, 1, u64> neg_pred;
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BitField<45, 1, u64> negate_b;
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BitField<46, 1, u64> abs_a;
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BitField<48, 1, u64> negate_a;
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BitField<49, 1, u64> abs_b;
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} const dmnmx{insn};
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const IR::U1 pred{v.ir.GetPred(dmnmx.pred)};
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const IR::F64 op_a{v.ir.FPAbsNeg(v.D(dmnmx.src_a_reg), dmnmx.abs_a != 0, dmnmx.negate_a != 0)};
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const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dmnmx.abs_b != 0, dmnmx.negate_b != 0)};
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IR::F64 max{v.ir.FPMax(op_a, op_b)};
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IR::F64 min{v.ir.FPMin(op_a, op_b)};
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if (dmnmx.neg_pred != 0) {
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std::swap(min, max);
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}
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v.D(dmnmx.dest_reg, IR::F64{v.ir.Select(pred, min, max)});
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}
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} // Anonymous namespace
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void TranslatorVisitor::DMNMX_reg(u64 insn) {
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DMNMX(*this, insn, GetDoubleReg20(insn));
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}
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void TranslatorVisitor::DMNMX_cbuf(u64 insn) {
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DMNMX(*this, insn, GetDoubleCbuf(insn));
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}
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void TranslatorVisitor::DMNMX_imm(u64 insn) {
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DMNMX(*this, insn, GetDoubleImm20(insn));
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}
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} // namespace Shader::Maxwell
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@ -0,0 +1,54 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/common_funcs.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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void DSETP(TranslatorVisitor& v, u64 insn, const IR::F64& src_b) {
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union {
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u64 insn;
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BitField<0, 3, IR::Pred> dest_pred_b;
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BitField<3, 3, IR::Pred> dest_pred_a;
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BitField<6, 1, u64> negate_b;
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BitField<7, 1, u64> abs_a;
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BitField<8, 8, IR::Reg> src_a_reg;
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BitField<39, 3, IR::Pred> bop_pred;
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BitField<42, 1, u64> neg_bop_pred;
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BitField<43, 1, u64> negate_a;
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BitField<44, 1, u64> abs_b;
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BitField<45, 2, BooleanOp> bop;
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BitField<48, 4, FPCompareOp> compare_op;
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} const dsetp{insn};
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const IR::F64 op_a{v.ir.FPAbsNeg(v.D(dsetp.src_a_reg), dsetp.abs_a != 0, dsetp.negate_a != 0)};
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const IR::F64 op_b{v.ir.FPAbsNeg(src_b, dsetp.abs_b != 0, dsetp.negate_b != 0)};
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const BooleanOp bop{dsetp.bop};
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const FPCompareOp compare_op{dsetp.compare_op};
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const IR::U1 comparison{FloatingPointCompare(v.ir, op_a, op_b, compare_op)};
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const IR::U1 bop_pred{v.ir.GetPred(dsetp.bop_pred, dsetp.neg_bop_pred != 0)};
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const IR::U1 result_a{PredicateCombine(v.ir, comparison, bop_pred, bop)};
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const IR::U1 result_b{PredicateCombine(v.ir, v.ir.LogicalNot(comparison), bop_pred, bop)};
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v.ir.SetPred(dsetp.dest_pred_a, result_a);
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v.ir.SetPred(dsetp.dest_pred_b, result_b);
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}
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} // Anonymous namespace
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void TranslatorVisitor::DSETP_reg(u64 insn) {
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DSETP(*this, insn, GetDoubleReg20(insn));
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}
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void TranslatorVisitor::DSETP_cbuf(u64 insn) {
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DSETP(*this, insn, GetDoubleCbuf(insn));
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}
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void TranslatorVisitor::DSETP_imm(u64 insn) {
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DSETP(*this, insn, GetDoubleImm20(insn));
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}
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} // namespace Shader::Maxwell
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