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@ -113,6 +113,7 @@ private:
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IR::Value ReadVariableRecursive(auto variable, IR::Block* block) {
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IR::Value val;
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if (const std::span preds{block->ImmediatePredecessors()}; preds.size() == 1) {
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// Optimize the common case of one predecessor: no phi needed
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val = ReadVariable(variable, preds.front());
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} else {
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// Break potential cycles with operandless phi
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@ -160,66 +161,70 @@ private:
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DefTable current_def;
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};
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void VisitInst(Pass& pass, IR::Block* block, IR::Inst& inst) {
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switch (inst.Opcode()) {
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case IR::Opcode::SetRegister:
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if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
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pass.WriteVariable(reg, block, inst.Arg(1));
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}
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break;
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case IR::Opcode::SetPred:
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if (const IR::Pred pred{inst.Arg(0).Pred()}; pred != IR::Pred::PT) {
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pass.WriteVariable(pred, block, inst.Arg(1));
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}
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break;
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case IR::Opcode::SetGotoVariable:
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pass.WriteVariable(GotoVariable{inst.Arg(0).U32()}, block, inst.Arg(1));
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break;
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case IR::Opcode::SetZFlag:
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pass.WriteVariable(ZeroFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::SetSFlag:
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pass.WriteVariable(SignFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::SetCFlag:
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pass.WriteVariable(CarryFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::SetOFlag:
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pass.WriteVariable(OverflowFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::GetRegister:
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if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
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inst.ReplaceUsesWith(pass.ReadVariable(reg, block));
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}
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break;
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case IR::Opcode::GetPred:
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if (const IR::Pred pred{inst.Arg(0).Pred()}; pred != IR::Pred::PT) {
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inst.ReplaceUsesWith(pass.ReadVariable(pred, block));
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}
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break;
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case IR::Opcode::GetGotoVariable:
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inst.ReplaceUsesWith(pass.ReadVariable(GotoVariable{inst.Arg(0).U32()}, block));
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break;
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case IR::Opcode::GetZFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(ZeroFlagTag{}, block));
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break;
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case IR::Opcode::GetSFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(SignFlagTag{}, block));
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break;
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case IR::Opcode::GetCFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(CarryFlagTag{}, block));
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break;
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case IR::Opcode::GetOFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(OverflowFlagTag{}, block));
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break;
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default:
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break;
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}
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}
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} // Anonymous namespace
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void SsaRewritePass(IR::Function& function) {
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Pass pass;
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for (IR::Block* const block : function.blocks) {
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for (IR::Inst& inst : block->Instructions()) {
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switch (inst.Opcode()) {
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case IR::Opcode::SetRegister:
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if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
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pass.WriteVariable(reg, block, inst.Arg(1));
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}
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break;
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case IR::Opcode::SetPred:
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if (const IR::Pred pred{inst.Arg(0).Pred()}; pred != IR::Pred::PT) {
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pass.WriteVariable(pred, block, inst.Arg(1));
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}
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break;
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case IR::Opcode::SetGotoVariable:
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pass.WriteVariable(GotoVariable{inst.Arg(0).U32()}, block, inst.Arg(1));
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break;
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case IR::Opcode::SetZFlag:
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pass.WriteVariable(ZeroFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::SetSFlag:
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pass.WriteVariable(SignFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::SetCFlag:
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pass.WriteVariable(CarryFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::SetOFlag:
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pass.WriteVariable(OverflowFlagTag{}, block, inst.Arg(0));
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break;
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case IR::Opcode::GetRegister:
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if (const IR::Reg reg{inst.Arg(0).Reg()}; reg != IR::Reg::RZ) {
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inst.ReplaceUsesWith(pass.ReadVariable(reg, block));
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}
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break;
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case IR::Opcode::GetPred:
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if (const IR::Pred pred{inst.Arg(0).Pred()}; pred != IR::Pred::PT) {
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inst.ReplaceUsesWith(pass.ReadVariable(pred, block));
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}
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break;
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case IR::Opcode::GetGotoVariable:
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inst.ReplaceUsesWith(pass.ReadVariable(GotoVariable{inst.Arg(0).U32()}, block));
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break;
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case IR::Opcode::GetZFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(ZeroFlagTag{}, block));
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break;
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case IR::Opcode::GetSFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(SignFlagTag{}, block));
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break;
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case IR::Opcode::GetCFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(CarryFlagTag{}, block));
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break;
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case IR::Opcode::GetOFlag:
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inst.ReplaceUsesWith(pass.ReadVariable(OverflowFlagTag{}, block));
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break;
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default:
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break;
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}
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VisitInst(pass, block, inst);
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}
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}
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}
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