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@ -5,6 +5,25 @@
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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void SetZeroFlag(EmitContext& ctx, IR::Inst* inst, Id result) {
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IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)};
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if (!zero) {
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return;
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}
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zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
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zero->Invalidate();
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}
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void SetSignFlag(EmitContext& ctx, IR::Inst* inst, Id result) {
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IR::Inst* const sign{inst->GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp)};
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if (!sign) {
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return;
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}
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sign->SetDefinition(ctx.OpSLessThan(ctx.U1, result, ctx.u32_zero_value));
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sign->Invalidate();
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}
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} // Anonymous namespace
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Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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Id result{};
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@ -19,14 +38,8 @@ Id EmitIAdd32(EmitContext& ctx, IR::Inst* inst, Id a, Id b) {
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} else {
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result = ctx.OpIAdd(ctx.U32[1], a, b);
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}
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if (IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)}) {
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zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
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zero->Invalidate();
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}
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if (IR::Inst* const sign{inst->GetAssociatedPseudoOperation(IR::Opcode::GetSignFromOp)}) {
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sign->SetDefinition(ctx.OpSLessThan(ctx.U1, result, ctx.u32_zero_value));
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sign->Invalidate();
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}
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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if (IR::Inst * overflow{inst->GetAssociatedPseudoOperation(IR::Opcode::GetOverflowFromOp)}) {
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// https://stackoverflow.com/questions/55468823/how-to-detect-integer-overflow-in-c
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constexpr u32 s32_max{static_cast<u32>(std::numeric_limits<s32>::max())};
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@ -114,16 +127,17 @@ Id EmitBitFieldInsert(EmitContext& ctx, Id base, Id insert, Id offset, Id count)
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return ctx.OpBitFieldInsert(ctx.U32[1], base, insert, offset, count);
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}
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Id EmitBitFieldSExtract(EmitContext& ctx, Id base, Id offset, Id count) {
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return ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count);
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Id EmitBitFieldSExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
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const Id result{ctx.OpBitFieldSExtract(ctx.U32[1], base, offset, count)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitBitFieldUExtract(EmitContext& ctx, IR::Inst* inst, Id base, Id offset, Id count) {
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const Id result{ctx.OpBitFieldUExtract(ctx.U32[1], base, offset, count)};
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if (IR::Inst* const zero{inst->GetAssociatedPseudoOperation(IR::Opcode::GetZeroFromOp)}) {
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zero->SetDefinition(ctx.OpIEqual(ctx.U1, result, ctx.u32_zero_value));
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zero->Invalidate();
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}
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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@ -163,12 +177,18 @@ Id EmitUMax32(EmitContext& ctx, Id a, Id b) {
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return ctx.OpUMax(ctx.U32[1], a, b);
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}
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Id EmitSClamp32(EmitContext& ctx, Id value, Id min, Id max) {
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return ctx.OpSClamp(ctx.U32[1], value, min, max);
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Id EmitSClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max) {
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const Id result{ctx.OpSClamp(ctx.U32[1], value, min, max)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitUClamp32(EmitContext& ctx, Id value, Id min, Id max) {
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return ctx.OpUClamp(ctx.U32[1], value, min, max);
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Id EmitUClamp32(EmitContext& ctx, IR::Inst* inst, Id value, Id min, Id max) {
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const Id result{ctx.OpUClamp(ctx.U32[1], value, min, max)};
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SetZeroFlag(ctx, inst, result);
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SetSignFlag(ctx, inst, result);
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return result;
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}
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Id EmitSLessThan(EmitContext& ctx, Id lhs, Id rhs) {
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