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@ -221,14 +221,11 @@ private:
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/// Generates code representing a temporary (GPR) register.
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std::string GetRegister(const Register& reg, unsigned elem = 0) {
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if (reg == Register::ZeroIndex)
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if (reg == Register::ZeroIndex) {
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return "0";
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment && reg < 4) {
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// GPRs 0-3 are output color for the fragment shader
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return std::string{"color."} + "rgba"[(reg + elem) & 3];
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}
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return *declr_register.insert("register_" + std::to_string(reg + elem)).first;
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return *declr_register.insert("register_" + std::to_string(reg.GetSwizzledIndex(elem)))
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.first;
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}
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/// Generates code representing a uniform (C buffer) register.
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@ -628,6 +625,15 @@ private:
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case OpCode::Id::EXIT: {
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ASSERT_MSG(instr.pred.pred_index == static_cast<u64>(Pred::UnusedIndex),
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"Predicated exits not implemented");
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// Final color output is currently hardcoded to GPR0-3 for fragment shaders
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if (stage == Maxwell3D::Regs::ShaderStage::Fragment) {
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shader.AddLine("color.r = " + GetRegister(0) + ";");
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shader.AddLine("color.g = " + GetRegister(1) + ";");
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shader.AddLine("color.b = " + GetRegister(2) + ";");
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shader.AddLine("color.a = " + GetRegister(3) + ";");
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}
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shader.AddLine("return true;");
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offset = PROGRAM_END - 1;
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break;
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