mirror of https://github.com/yuzu-mirror/yuzu
shader: Implement SHFL
ameerj
4 years ago
parent
49e87ea8ab
commit
32c5483beb
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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Id LargeWarpBallot(EmitContext& ctx, Id ballot) {
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const Id shift{ctx.Constant(ctx.U32[1], 5)};
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const Id local_index{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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return ctx.OpVectorExtractDynamic(ctx.U32[1], ballot, local_index);
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}
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} // Anonymous namespace
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Id EmitVoteAll(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAllKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpIEqual(ctx.U1, lhs, active_mask);
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}
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Id EmitVoteAny(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAnyKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpINotEqual(ctx.U1, lhs, ctx.u32_zero_value);
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}
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Id EmitVoteEqual(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAllEqualKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseXor(ctx.U32[1], ballot, active_mask)};
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return ctx.OpLogicalOr(ctx.U1, ctx.OpIEqual(ctx.U1, lhs, ctx.u32_zero_value),
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ctx.OpIEqual(ctx.U1, lhs, active_mask));
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}
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Id EmitSubgroupBallot(EmitContext& ctx, Id pred) {
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const Id ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], pred)};
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpCompositeExtract(ctx.U32[1], ballot, 0U);
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}
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return LargeWarpBallot(ctx, ballot);
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}
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} // namespace Shader::Backend::SPIRV
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@ -0,0 +1,135 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include "shader_recompiler/backend/spirv/emit_spirv.h"
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namespace Shader::Backend::SPIRV {
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namespace {
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Id LargeWarpBallot(EmitContext& ctx, Id ballot) {
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const Id shift{ctx.Constant(ctx.U32[1], 5)};
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const Id local_index{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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return ctx.OpVectorExtractDynamic(ctx.U32[1], ballot, local_index);
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}
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void SetInBoundsFlag(IR::Inst* inst, Id result) {
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IR::Inst* const in_bounds{inst->GetAssociatedPseudoOperation(IR::Opcode::GetInBoundsFromOp)};
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if (!in_bounds) {
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return;
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}
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in_bounds->SetDefinition(result);
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in_bounds->Invalidate();
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}
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Id ComputeMinThreadId(EmitContext& ctx, Id thread_id, Id segmentation_mask) {
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return ctx.OpBitwiseAnd(ctx.U32[1], thread_id, segmentation_mask);
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}
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Id ComputeMaxThreadId(EmitContext& ctx, Id min_thread_id, Id clamp, Id not_seg_mask) {
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return ctx.OpBitwiseOr(ctx.U32[1], min_thread_id,
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ctx.OpBitwiseAnd(ctx.U32[1], clamp, not_seg_mask));
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}
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Id GetMaxThreadId(EmitContext& ctx, Id thread_id, Id clamp, Id segmentation_mask) {
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const Id not_seg_mask{ctx.OpNot(ctx.U32[1], segmentation_mask)};
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const Id min_thread_id{ComputeMinThreadId(ctx, thread_id, segmentation_mask)};
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return ComputeMaxThreadId(ctx, min_thread_id, clamp, not_seg_mask);
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}
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Id SelectValue(EmitContext& ctx, Id in_range, Id value, Id src_thread_id) {
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return ctx.OpSelect(ctx.U32[1], in_range,
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ctx.OpSubgroupReadInvocationKHR(ctx.U32[1], value, src_thread_id), value);
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}
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} // Anonymous namespace
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Id EmitVoteAll(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAllKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpIEqual(ctx.U1, lhs, active_mask);
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}
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Id EmitVoteAny(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAnyKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], ballot, active_mask)};
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return ctx.OpINotEqual(ctx.U1, lhs, ctx.u32_zero_value);
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}
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Id EmitVoteEqual(EmitContext& ctx, Id pred) {
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpSubgroupAllEqualKHR(ctx.U1, pred);
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}
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const Id mask_ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], ctx.true_value)};
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const Id active_mask{LargeWarpBallot(ctx, mask_ballot)};
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const Id ballot{LargeWarpBallot(ctx, ctx.OpSubgroupBallotKHR(ctx.U32[4], pred))};
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const Id lhs{ctx.OpBitwiseXor(ctx.U32[1], ballot, active_mask)};
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return ctx.OpLogicalOr(ctx.U1, ctx.OpIEqual(ctx.U1, lhs, ctx.u32_zero_value),
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ctx.OpIEqual(ctx.U1, lhs, active_mask));
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}
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Id EmitSubgroupBallot(EmitContext& ctx, Id pred) {
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const Id ballot{ctx.OpSubgroupBallotKHR(ctx.U32[4], pred)};
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if (!ctx.profile.warp_size_potentially_larger_than_guest) {
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return ctx.OpCompositeExtract(ctx.U32[1], ballot, 0U);
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}
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return LargeWarpBallot(ctx, ballot);
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}
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Id EmitShuffleIndex(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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const Id not_seg_mask{ctx.OpNot(ctx.U32[1], segmentation_mask)};
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const Id thread_id{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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const Id min_thread_id{ComputeMinThreadId(ctx, thread_id, segmentation_mask)};
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const Id max_thread_id{ComputeMaxThreadId(ctx, min_thread_id, clamp, not_seg_mask)};
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const Id lhs{ctx.OpBitwiseAnd(ctx.U32[1], index, not_seg_mask)};
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const Id src_thread_id{ctx.OpBitwiseOr(ctx.U32[1], lhs, min_thread_id)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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Id EmitShuffleUp(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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const Id thread_id{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id src_thread_id{ctx.OpISub(ctx.U32[1], thread_id, index)};
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const Id in_range{ctx.OpSGreaterThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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Id EmitShuffleDown(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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const Id thread_id{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id src_thread_id{ctx.OpIAdd(ctx.U32[1], thread_id, index)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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Id EmitShuffleButterfly(EmitContext& ctx, IR::Inst* inst, Id value, Id index, Id clamp,
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Id segmentation_mask) {
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const Id thread_id{ctx.OpLoad(ctx.U32[1], ctx.subgroup_local_invocation_id)};
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const Id max_thread_id{GetMaxThreadId(ctx, thread_id, clamp, segmentation_mask)};
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const Id src_thread_id{ctx.OpBitwiseXor(ctx.U32[1], thread_id, index)};
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const Id in_range{ctx.OpSLessThanEqual(ctx.U1, src_thread_id, max_thread_id)};
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SetInBoundsFlag(inst, in_range);
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return SelectValue(ctx, in_range, value, src_thread_id);
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}
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} // namespace Shader::Backend::SPIRV
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@ -0,0 +1,69 @@
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// Copyright 2021 yuzu Emulator Project
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// Licensed under GPLv2 or any later version
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// Refer to the license.txt file included.
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#include <optional>
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#include "common/bit_field.h"
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#include "common/common_types.h"
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#include "shader_recompiler/frontend/maxwell/translate/impl/impl.h"
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namespace Shader::Maxwell {
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namespace {
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enum class ShuffleMode : u64 {
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IDX,
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UP,
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DOWN,
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BFLY,
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};
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[[nodiscard]] IR::U32 ShuffleOperation(IR::IREmitter& ir, const IR::U32& value,
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const IR::U32& index, const IR::U32& mask,
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ShuffleMode shfl_op) {
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const IR::U32 clamp{ir.BitFieldExtract(mask, ir.Imm32(0), ir.Imm32(5))};
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const IR::U32 seg_mask{ir.BitFieldExtract(mask, ir.Imm32(8), ir.Imm32(5))};
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switch (shfl_op) {
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case ShuffleMode::IDX:
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return ir.ShuffleIndex(value, index, clamp, seg_mask);
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case ShuffleMode::UP:
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return ir.ShuffleUp(value, index, clamp, seg_mask);
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case ShuffleMode::DOWN:
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return ir.ShuffleDown(value, index, clamp, seg_mask);
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case ShuffleMode::BFLY:
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return ir.ShuffleButterfly(value, index, clamp, seg_mask);
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default:
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throw NotImplementedException("Invalid SHFL op {}", shfl_op);
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}
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}
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void Shuffle(TranslatorVisitor& v, u64 insn, const IR::U32& index, const IR::U32& mask) {
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union {
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u64 insn;
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BitField<0, 8, IR::Reg> dest_reg;
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BitField<8, 8, IR::Reg> src_reg;
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BitField<30, 2, ShuffleMode> mode;
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BitField<48, 3, IR::Pred> pred;
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} const shfl{insn};
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const IR::U32 result{ShuffleOperation(v.ir, v.X(shfl.src_reg), index, mask, shfl.mode)};
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v.ir.SetPred(shfl.pred, v.ir.GetInBoundsFromOp(result));
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v.X(shfl.dest_reg, result);
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}
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} // Anonymous namespace
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void TranslatorVisitor::SHFL(u64 insn) {
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union {
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u64 insn;
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BitField<20, 5, u64> src_a_imm;
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BitField<28, 1, u64> src_a_flag;
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BitField<29, 1, u64> src_b_flag;
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BitField<34, 13, u64> src_b_imm;
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} const flags{insn};
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const IR::U32 src_a{flags.src_a_flag != 0 ? ir.Imm32(static_cast<u32>(flags.src_a_imm))
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: GetReg20(insn)};
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const IR::U32 src_b{flags.src_b_flag != 0 ? ir.Imm32(static_cast<u32>(flags.src_b_imm))
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: GetReg39(insn)};
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Shuffle(*this, insn, src_a, src_b);
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}
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} // namespace Shader::Maxwell
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