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@ -146,12 +146,25 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::LD:
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case OpCode::Id::LDG: {
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const auto type = [instr, &opcode]() -> Tegra::Shader::UniformType {
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switch (opcode->get().GetId()) {
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case OpCode::Id::LD:
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UNIMPLEMENTED_IF_MSG(!instr.generic.extended, "Unextended LD is not implemented");
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return instr.generic.type;
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case OpCode::Id::LDG:
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return instr.ldg.type;
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default:
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UNREACHABLE();
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return {};
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}
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}();
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const auto [real_address_base, base_address, descriptor] =
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TrackAndGetGlobalMemory(bb, GetRegister(instr.gpr8),
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static_cast<u32>(instr.ldg.immediate_offset.Value()), false);
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TrackAndGetGlobalMemory(bb, instr, false);
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const u32 count = GetUniformTypeElementsCount(instr.ldg.type);
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const u32 count = GetUniformTypeElementsCount(type);
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for (u32 i = 0; i < count; ++i) {
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const Node it_offset = Immediate(i * 4);
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const Node real_address =
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@ -165,28 +178,6 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::STG: {
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const auto [real_address_base, base_address, descriptor] =
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TrackAndGetGlobalMemory(bb, GetRegister(instr.gpr8),
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static_cast<u32>(instr.stg.immediate_offset.Value()), true);
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// Encode in temporary registers like this: real_base_address, {registers_to_be_written...}
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SetTemporal(bb, 0, real_address_base);
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const u32 count = GetUniformTypeElementsCount(instr.stg.type);
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for (u32 i = 0; i < count; ++i) {
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SetTemporal(bb, i + 1, GetRegister(instr.gpr0.Value() + i));
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}
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for (u32 i = 0; i < count; ++i) {
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const Node it_offset = Immediate(i * 4);
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const Node real_address =
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Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
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const Node gmem = StoreNode(GmemNode(real_address, base_address, descriptor));
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bb.push_back(Operation(OperationCode::Assign, gmem, GetTemporal(i + 1)));
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}
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break;
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}
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case OpCode::Id::ST_A: {
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UNIMPLEMENTED_IF_MSG(instr.gpr8.Value() != Register::ZeroIndex,
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"Indirect attribute loads are not supported");
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@ -242,6 +233,41 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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}
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break;
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}
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case OpCode::Id::ST:
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case OpCode::Id::STG: {
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const auto type = [instr, &opcode]() -> Tegra::Shader::UniformType {
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switch (opcode->get().GetId()) {
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case OpCode::Id::ST:
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UNIMPLEMENTED_IF_MSG(!instr.generic.extended, "Unextended ST is not implemented");
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return instr.generic.type;
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case OpCode::Id::STG:
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return instr.stg.type;
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default:
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UNREACHABLE();
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return {};
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}
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}();
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const auto [real_address_base, base_address, descriptor] =
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TrackAndGetGlobalMemory(bb, instr, true);
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// Encode in temporary registers like this: real_base_address, {registers_to_be_written...}
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SetTemporal(bb, 0, real_address_base);
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const u32 count = GetUniformTypeElementsCount(type);
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for (u32 i = 0; i < count; ++i) {
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SetTemporal(bb, i + 1, GetRegister(instr.gpr0.Value() + i));
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}
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for (u32 i = 0; i < count; ++i) {
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const Node it_offset = Immediate(i * 4);
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const Node real_address =
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Operation(OperationCode::UAdd, NO_PRECISE, real_address_base, it_offset);
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const Node gmem = StoreNode(GmemNode(real_address, base_address, descriptor));
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bb.push_back(Operation(OperationCode::Assign, gmem, GetTemporal(i + 1)));
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}
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break;
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}
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case OpCode::Id::AL2P: {
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// Ignore al2p.direction since we don't care about it.
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@ -265,9 +291,11 @@ u32 ShaderIR::DecodeMemory(NodeBlock& bb, u32 pc) {
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}
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std::tuple<Node, Node, GlobalMemoryBase> ShaderIR::TrackAndGetGlobalMemory(NodeBlock& bb,
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Node addr_register,
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u32 immediate_offset,
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Instruction instr,
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bool is_write) {
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const auto addr_register{GetRegister(instr.gmem.gpr)};
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const auto immediate_offset{static_cast<u32>(instr.gmem.offset)};
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const Node base_address{
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TrackCbuf(addr_register, global_code, static_cast<s64>(global_code.size()))};
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const auto cbuf = std::get_if<CbufNode>(base_address);
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