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472 lines
17 KiB
C++
472 lines
17 KiB
C++
// SPDX-FileCopyrightText: Copyright 2023 yuzu Emulator Project
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// SPDX-License-Identifier: GPL-2.0-or-later
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#include "common/arm64/native_clock.h"
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#include "common/bit_cast.h"
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#include "common/literals.h"
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#include "core/arm/nce/arm_nce.h"
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#include "core/arm/nce/guest_context.h"
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#include "core/arm/nce/instructions.h"
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#include "core/arm/nce/patch.h"
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#include "core/core.h"
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#include "core/core_timing.h"
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#include "core/hle/kernel/svc.h"
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namespace Core::NCE {
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using namespace Common::Literals;
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using namespace oaknut::util;
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using NativeExecutionParameters = Kernel::KThread::NativeExecutionParameters;
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constexpr size_t MaxRelativeBranch = 128_MiB;
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Patcher::Patcher() : c(m_patch_instructions) {}
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Patcher::~Patcher() = default;
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void Patcher::PatchText(const Kernel::PhysicalMemory& program_image,
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const Kernel::CodeSet::Segment& code) {
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// Write save context helper function.
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c.l(m_save_context);
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WriteSaveContext();
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// Write load context helper function.
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c.l(m_load_context);
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WriteLoadContext();
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// Retrieve text segment data.
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const auto text = std::span{program_image}.subspan(code.offset, code.size);
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const auto text_words =
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std::span<const u32>{reinterpret_cast<const u32*>(text.data()), text.size() / sizeof(u32)};
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// Loop through instructions, patching as needed.
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for (u32 i = 0; i < static_cast<u32>(text_words.size()); i++) {
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const u32 inst = text_words[i];
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const auto AddRelocations = [&] {
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const uintptr_t this_offset = i * sizeof(u32);
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const uintptr_t next_offset = this_offset + sizeof(u32);
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// Relocate from here to patch.
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this->BranchToPatch(this_offset);
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// Relocate from patch to next instruction.
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return next_offset;
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};
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// SVC
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if (auto svc = SVC{inst}; svc.Verify()) {
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WriteSvcTrampoline(AddRelocations(), svc.GetValue());
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continue;
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}
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// MRS Xn, TPIDR_EL0
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// MRS Xn, TPIDRRO_EL0
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if (auto mrs = MRS{inst};
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mrs.Verify() && (mrs.GetSystemReg() == TpidrroEl0 || mrs.GetSystemReg() == TpidrEl0)) {
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const auto src_reg = mrs.GetSystemReg() == TpidrroEl0 ? oaknut::SystemReg::TPIDRRO_EL0
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: oaknut::SystemReg::TPIDR_EL0;
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const auto dest_reg = oaknut::XReg{static_cast<int>(mrs.GetRt())};
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WriteMrsHandler(AddRelocations(), dest_reg, src_reg);
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continue;
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}
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// MRS Xn, CNTPCT_EL0
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if (auto mrs = MRS{inst}; mrs.Verify() && mrs.GetSystemReg() == CntpctEl0) {
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WriteCntpctHandler(AddRelocations(), oaknut::XReg{static_cast<int>(mrs.GetRt())});
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continue;
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}
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// MRS Xn, CNTFRQ_EL0
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if (auto mrs = MRS{inst}; mrs.Verify() && mrs.GetSystemReg() == CntfrqEl0) {
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UNREACHABLE();
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}
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// MSR TPIDR_EL0, Xn
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if (auto msr = MSR{inst}; msr.Verify() && msr.GetSystemReg() == TpidrEl0) {
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WriteMsrHandler(AddRelocations(), oaknut::XReg{static_cast<int>(msr.GetRt())});
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continue;
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}
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}
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// Determine patching mode for the final relocation step
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const size_t image_size = program_image.size();
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this->mode = image_size > MaxRelativeBranch ? PatchMode::PreText : PatchMode::PostData;
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}
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void Patcher::RelocateAndCopy(Common::ProcessAddress load_base,
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const Kernel::CodeSet::Segment& code,
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Kernel::PhysicalMemory& program_image,
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EntryTrampolines* out_trampolines) {
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const size_t patch_size = GetSectionSize();
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const size_t image_size = program_image.size();
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// Retrieve text segment data.
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const auto text = std::span{program_image}.subspan(code.offset, code.size);
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const auto text_words =
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std::span<u32>{reinterpret_cast<u32*>(text.data()), text.size() / sizeof(u32)};
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const auto ApplyBranchToPatchRelocation = [&](u32* target, const Relocation& rel) {
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oaknut::CodeGenerator rc{target};
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if (mode == PatchMode::PreText) {
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rc.B(rel.patch_offset - patch_size - rel.module_offset);
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} else {
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rc.B(image_size - rel.module_offset + rel.patch_offset);
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}
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};
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const auto ApplyBranchToModuleRelocation = [&](u32* target, const Relocation& rel) {
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oaknut::CodeGenerator rc{target};
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if (mode == PatchMode::PreText) {
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rc.B(patch_size - rel.patch_offset + rel.module_offset);
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} else {
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rc.B(rel.module_offset - image_size - rel.patch_offset);
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}
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};
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const auto RebasePatch = [&](ptrdiff_t patch_offset) {
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if (mode == PatchMode::PreText) {
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return GetInteger(load_base) + patch_offset;
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} else {
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return GetInteger(load_base) + image_size + patch_offset;
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}
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};
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const auto RebasePc = [&](uintptr_t module_offset) {
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if (mode == PatchMode::PreText) {
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return GetInteger(load_base) + patch_size + module_offset;
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} else {
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return GetInteger(load_base) + module_offset;
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}
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};
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// We are now ready to relocate!
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for (const Relocation& rel : m_branch_to_patch_relocations) {
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ApplyBranchToPatchRelocation(text_words.data() + rel.module_offset / sizeof(u32), rel);
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}
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for (const Relocation& rel : m_branch_to_module_relocations) {
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ApplyBranchToModuleRelocation(m_patch_instructions.data() + rel.patch_offset / sizeof(u32),
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rel);
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}
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// Rewrite PC constants and record post trampolines
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for (const Relocation& rel : m_write_module_pc_relocations) {
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oaknut::CodeGenerator rc{m_patch_instructions.data() + rel.patch_offset / sizeof(u32)};
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rc.dx(RebasePc(rel.module_offset));
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}
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for (const Trampoline& rel : m_trampolines) {
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out_trampolines->insert({RebasePc(rel.module_offset), RebasePatch(rel.patch_offset)});
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}
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// Cortex-A57 seems to treat all exclusives as ordered, but newer processors do not.
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// Convert to ordered to preserve this assumption
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for (u32 i = 0; i < static_cast<u32>(text_words.size()); i++) {
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const u32 inst = text_words[i];
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if (auto exclusive = Exclusive{inst}; exclusive.Verify()) {
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text_words[i] = exclusive.AsOrdered();
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}
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}
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// Copy to program image
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if (this->mode == PatchMode::PreText) {
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std::memcpy(program_image.data(), m_patch_instructions.data(),
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m_patch_instructions.size() * sizeof(u32));
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} else {
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program_image.resize(image_size + patch_size);
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std::memcpy(program_image.data() + image_size, m_patch_instructions.data(),
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m_patch_instructions.size() * sizeof(u32));
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}
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}
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size_t Patcher::GetSectionSize() const noexcept {
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return Common::AlignUp(m_patch_instructions.size() * sizeof(u32), Core::Memory::YUZU_PAGESIZE);
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}
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void Patcher::WriteLoadContext() {
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// This function was called, which modifies X30, so use that as a scratch register.
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// SP contains the guest X30, so save our return X30 to SP + 8, since we have allocated 16 bytes
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// of stack.
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c.STR(X30, SP, 8);
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c.MRS(X30, oaknut::SystemReg::TPIDR_EL0);
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c.LDR(X30, X30, offsetof(NativeExecutionParameters, native_context));
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// Load system registers.
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c.LDR(W0, X30, offsetof(GuestContext, fpsr));
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c.MSR(oaknut::SystemReg::FPSR, X0);
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c.LDR(W0, X30, offsetof(GuestContext, fpcr));
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c.MSR(oaknut::SystemReg::FPCR, X0);
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c.LDR(W0, X30, offsetof(GuestContext, nzcv));
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c.MSR(oaknut::SystemReg::NZCV, X0);
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// Load all vector registers.
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static constexpr size_t VEC_OFF = offsetof(GuestContext, vector_registers);
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for (int i = 0; i <= 30; i += 2) {
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c.LDP(oaknut::QReg{i}, oaknut::QReg{i + 1}, X30, VEC_OFF + 16 * i);
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}
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// Load all general-purpose registers except X30.
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for (int i = 0; i <= 28; i += 2) {
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c.LDP(oaknut::XReg{i}, oaknut::XReg{i + 1}, X30, 8 * i);
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}
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// Reload our return X30 from the stack and return.
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// The patch code will reload the guest X30 for us.
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c.LDR(X30, SP, 8);
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c.RET();
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}
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void Patcher::WriteSaveContext() {
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// This function was called, which modifies X30, so use that as a scratch register.
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// SP contains the guest X30, so save our X30 to SP + 8, since we have allocated 16 bytes of
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// stack.
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c.STR(X30, SP, 8);
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c.MRS(X30, oaknut::SystemReg::TPIDR_EL0);
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c.LDR(X30, X30, offsetof(NativeExecutionParameters, native_context));
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// Store all general-purpose registers except X30.
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for (int i = 0; i <= 28; i += 2) {
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c.STP(oaknut::XReg{i}, oaknut::XReg{i + 1}, X30, 8 * i);
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}
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// Store all vector registers.
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static constexpr size_t VEC_OFF = offsetof(GuestContext, vector_registers);
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for (int i = 0; i <= 30; i += 2) {
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c.STP(oaknut::QReg{i}, oaknut::QReg{i + 1}, X30, VEC_OFF + 16 * i);
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}
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// Store guest system registers, X30 and SP, using X0 as a scratch register.
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c.STR(X0, SP, PRE_INDEXED, -16);
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c.LDR(X0, SP, 16);
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c.STR(X0, X30, 8 * 30);
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c.ADD(X0, SP, 32);
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c.STR(X0, X30, offsetof(GuestContext, sp));
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c.MRS(X0, oaknut::SystemReg::FPSR);
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c.STR(W0, X30, offsetof(GuestContext, fpsr));
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c.MRS(X0, oaknut::SystemReg::FPCR);
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c.STR(W0, X30, offsetof(GuestContext, fpcr));
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c.MRS(X0, oaknut::SystemReg::NZCV);
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c.STR(W0, X30, offsetof(GuestContext, nzcv));
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c.LDR(X0, SP, POST_INDEXED, 16);
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// Reload our return X30 from the stack, and return.
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c.LDR(X30, SP, 8);
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c.RET();
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}
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void Patcher::WriteSvcTrampoline(ModuleDestLabel module_dest, u32 svc_id) {
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// We are about to start saving state, so we need to lock the context.
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this->LockContext();
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// Store guest X30 to the stack. Then, save the context and restore the stack.
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// This will save all registers except PC, but we know PC at patch time.
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c.STR(X30, SP, PRE_INDEXED, -16);
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c.BL(m_save_context);
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c.LDR(X30, SP, POST_INDEXED, 16);
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// Now that we've saved all registers, we can use any registers as scratch.
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// Store PC + 4 to arm interface, since we know the instruction offset from the entry point.
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oaknut::Label pc_after_svc;
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c.MRS(X1, oaknut::SystemReg::TPIDR_EL0);
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c.LDR(X1, X1, offsetof(NativeExecutionParameters, native_context));
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c.LDR(X2, pc_after_svc);
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c.STR(X2, X1, offsetof(GuestContext, pc));
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// Store SVC number to execute when we return
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c.MOV(X2, svc_id);
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c.STR(W2, X1, offsetof(GuestContext, svc_swi));
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// We are calling a SVC. Clear esr_el1 and return it.
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static_assert(std::is_same_v<std::underlying_type_t<HaltReason>, u64>);
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oaknut::Label retry;
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c.ADD(X2, X1, offsetof(GuestContext, esr_el1));
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c.l(retry);
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c.LDAXR(X0, X2);
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c.STLXR(W3, XZR, X2);
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c.CBNZ(W3, retry);
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// Add "calling SVC" flag. Since this is X0, this is now our return value.
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c.ORR(X0, X0, static_cast<u64>(HaltReason::SupervisorCall));
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// Offset the GuestContext pointer to the HostContext member.
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// STP has limited range of [-512, 504] which we can't reach otherwise
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// NB: Due to this all offsets below are from the start of HostContext.
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c.ADD(X1, X1, offsetof(GuestContext, host_ctx));
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// Reload host TPIDR_EL0 and SP.
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static_assert(offsetof(HostContext, host_sp) + 8 == offsetof(HostContext, host_tpidr_el0));
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c.LDP(X2, X3, X1, offsetof(HostContext, host_sp));
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c.MOV(SP, X2);
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c.MSR(oaknut::SystemReg::TPIDR_EL0, X3);
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// Load callee-saved host registers and return to host.
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static constexpr size_t HOST_REGS_OFF = offsetof(HostContext, host_saved_regs);
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static constexpr size_t HOST_VREGS_OFF = offsetof(HostContext, host_saved_vregs);
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c.LDP(X19, X20, X1, HOST_REGS_OFF);
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c.LDP(X21, X22, X1, HOST_REGS_OFF + 2 * sizeof(u64));
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c.LDP(X23, X24, X1, HOST_REGS_OFF + 4 * sizeof(u64));
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c.LDP(X25, X26, X1, HOST_REGS_OFF + 6 * sizeof(u64));
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c.LDP(X27, X28, X1, HOST_REGS_OFF + 8 * sizeof(u64));
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c.LDP(X29, X30, X1, HOST_REGS_OFF + 10 * sizeof(u64));
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c.LDP(Q8, Q9, X1, HOST_VREGS_OFF);
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c.LDP(Q10, Q11, X1, HOST_VREGS_OFF + 2 * sizeof(u128));
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c.LDP(Q12, Q13, X1, HOST_VREGS_OFF + 4 * sizeof(u128));
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c.LDP(Q14, Q15, X1, HOST_VREGS_OFF + 6 * sizeof(u128));
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c.RET();
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// Write the post-SVC trampoline address, which will jump back to the guest after restoring its
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// state.
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m_trampolines.push_back({c.offset(), module_dest});
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// Host called this location. Save the return address so we can
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// unwind the stack properly when jumping back.
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c.MRS(X2, oaknut::SystemReg::TPIDR_EL0);
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c.LDR(X2, X2, offsetof(NativeExecutionParameters, native_context));
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c.ADD(X0, X2, offsetof(GuestContext, host_ctx));
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c.STR(X30, X0, offsetof(HostContext, host_saved_regs) + 11 * sizeof(u64));
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// Reload all guest registers except X30 and PC.
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// The function also expects 16 bytes of stack already allocated.
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c.STR(X30, SP, PRE_INDEXED, -16);
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c.BL(m_load_context);
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c.LDR(X30, SP, POST_INDEXED, 16);
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// Use X1 as a scratch register to restore X30.
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c.STR(X1, SP, PRE_INDEXED, -16);
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c.MRS(X1, oaknut::SystemReg::TPIDR_EL0);
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c.LDR(X1, X1, offsetof(NativeExecutionParameters, native_context));
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c.LDR(X30, X1, offsetof(GuestContext, cpu_registers) + sizeof(u64) * 30);
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c.LDR(X1, SP, POST_INDEXED, 16);
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// Unlock the context.
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this->UnlockContext();
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// Jump back to the instruction after the emulated SVC.
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this->BranchToModule(module_dest);
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// Store PC after call.
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c.l(pc_after_svc);
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this->WriteModulePc(module_dest);
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}
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void Patcher::WriteMrsHandler(ModuleDestLabel module_dest, oaknut::XReg dest_reg,
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oaknut::SystemReg src_reg) {
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// Retrieve emulated TLS register from GuestContext.
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c.MRS(dest_reg, oaknut::SystemReg::TPIDR_EL0);
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if (src_reg == oaknut::SystemReg::TPIDRRO_EL0) {
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c.LDR(dest_reg, dest_reg, offsetof(NativeExecutionParameters, tpidrro_el0));
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} else {
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c.LDR(dest_reg, dest_reg, offsetof(NativeExecutionParameters, tpidr_el0));
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}
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// Jump back to the instruction after the emulated MRS.
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this->BranchToModule(module_dest);
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}
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void Patcher::WriteMsrHandler(ModuleDestLabel module_dest, oaknut::XReg src_reg) {
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const auto scratch_reg = src_reg.index() == 0 ? X1 : X0;
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c.STR(scratch_reg, SP, PRE_INDEXED, -16);
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// Save guest value to NativeExecutionParameters::tpidr_el0.
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c.MRS(scratch_reg, oaknut::SystemReg::TPIDR_EL0);
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c.STR(src_reg, scratch_reg, offsetof(NativeExecutionParameters, tpidr_el0));
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// Restore scratch register.
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c.LDR(scratch_reg, SP, POST_INDEXED, 16);
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// Jump back to the instruction after the emulated MSR.
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this->BranchToModule(module_dest);
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}
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void Patcher::WriteCntpctHandler(ModuleDestLabel module_dest, oaknut::XReg dest_reg) {
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static Common::Arm64::NativeClock clock{};
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const auto factor = clock.GetGuestCNTFRQFactor();
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const auto raw_factor = Common::BitCast<std::array<u64, 2>>(factor);
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const auto use_x2_x3 = dest_reg.index() == 0 || dest_reg.index() == 1;
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oaknut::XReg scratch0 = use_x2_x3 ? X2 : X0;
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oaknut::XReg scratch1 = use_x2_x3 ? X3 : X1;
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oaknut::Label factorlo;
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oaknut::Label factorhi;
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// Save scratches.
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c.STP(scratch0, scratch1, SP, PRE_INDEXED, -16);
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// Load counter value.
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c.MRS(dest_reg, oaknut::SystemReg::CNTVCT_EL0);
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// Load scaling factor.
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c.LDR(scratch0, factorlo);
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c.LDR(scratch1, factorhi);
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// Multiply low bits and get result.
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c.UMULH(scratch0, dest_reg, scratch0);
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// Multiply high bits and add low bit result.
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c.MADD(dest_reg, dest_reg, scratch1, scratch0);
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// Reload scratches.
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c.LDP(scratch0, scratch1, SP, POST_INDEXED, 16);
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// Jump back to the instruction after the emulated MRS.
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this->BranchToModule(module_dest);
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// Scaling factor constant values.
|
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c.l(factorlo);
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c.dx(raw_factor[0]);
|
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c.l(factorhi);
|
|
c.dx(raw_factor[1]);
|
|
}
|
|
|
|
void Patcher::LockContext() {
|
|
oaknut::Label retry;
|
|
|
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// Save scratches.
|
|
c.STP(X0, X1, SP, PRE_INDEXED, -16);
|
|
|
|
// Reload lock pointer.
|
|
c.l(retry);
|
|
c.CLREX();
|
|
c.MRS(X0, oaknut::SystemReg::TPIDR_EL0);
|
|
c.ADD(X0, X0, offsetof(NativeExecutionParameters, lock));
|
|
|
|
static_assert(SpinLockLocked == 0);
|
|
|
|
// Load-linked with acquire ordering.
|
|
c.LDAXR(W1, X0);
|
|
|
|
// If the value was SpinLockLocked, clear monitor and retry.
|
|
c.CBZ(W1, retry);
|
|
|
|
// Store-conditional SpinLockLocked with relaxed ordering.
|
|
c.STXR(W1, WZR, X0);
|
|
|
|
// If we failed to store, retry.
|
|
c.CBNZ(W1, retry);
|
|
|
|
// We succeeded! Reload scratches.
|
|
c.LDP(X0, X1, SP, POST_INDEXED, 16);
|
|
}
|
|
|
|
void Patcher::UnlockContext() {
|
|
// Save scratches.
|
|
c.STP(X0, X1, SP, PRE_INDEXED, -16);
|
|
|
|
// Load lock pointer.
|
|
c.MRS(X0, oaknut::SystemReg::TPIDR_EL0);
|
|
c.ADD(X0, X0, offsetof(NativeExecutionParameters, lock));
|
|
|
|
// Load SpinLockUnlocked.
|
|
c.MOV(W1, SpinLockUnlocked);
|
|
|
|
// Store value with release ordering.
|
|
c.STLR(W1, X0);
|
|
|
|
// Load scratches.
|
|
c.LDP(X0, X1, SP, POST_INDEXED, 16);
|
|
}
|
|
|
|
} // namespace Core::NCE
|