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94 lines
1.8 KiB
Makefile
94 lines
1.8 KiB
Makefile
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#GCC = mips64-sb1sim-gcc -DDBG -DBCMDBG
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GCC = mips64-sb1sim-gcc
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GLD = mips64-sb1sim-ld
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AR = mips64-sb1sim-ar
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OBJDUMP = mips64-sb1sim-objdump
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OBJCOPY = mips64-sb1sim-objcopy
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RANLIB = mips64-sb1sim-ranlib
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CFG_MLONG64 ?= 0
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# Uncomment to boot from PCI/JTAG
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#CFG_EPIBOOT=1
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# Note: Big endian is not likely to work without some
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# major source changes in the drivers.
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# Note: this configuration is for loading into FLASH via
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# Epidiag
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# Link & Run uncached (Quickturn ala Epidiag/JTAG)
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ifeq ($(CFG_EPIBOOT),1)
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CFG_LITTLE ?= 1
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CFG_RELOC ?= 0
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CFG_UNCACHED ?= 1
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CFG_VAPI ?= 0
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CFG_BOOTRAM ?= 1
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CFG_UNCACHED_RAMAPP ?= 1
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CFG_BOARDNAME = "BU4704"
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# For JTAG Boot, uncomment this line
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CFLAGS += -DJTAG_RAM_BOOT
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#CFG_MINIMAL_SIZE=1
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CFG_MINIMAL_SIZE=0
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else
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# Note: this configuration is for loading into FLASH via
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# Epidiag via "s flashutl.tcl" and "flwritefile cfe.bin"
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# Link and Run cached (Note: will not work from Epidiag)
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CFG_LITTLE ?= 1
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CFG_RELOC ?= 1
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CFG_UNCACHED ?= 0
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CFG_VAPI ?= 0
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CFG_BOOTRAM ?= 0
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CFG_BOARDNAME = "BU4704"
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CFG_PCI = 0
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CFG_MSYS = 0
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CFG_MINIMAL_SIZE=0
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endif
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# Define the CPU family
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CFLAGS += -DMIPS33xx
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CFLAGS += -DBCM4704
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# Define for building 4704
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CFG_4704 = 1
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# For DDR SDRAM
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CFLAGS += -DDDRAM
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# Disable Flow control on UART
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CFLAGS += -DNS16550_NO_FLOW
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CFG_PCI = 0
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CFG_ZLIB=1
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CFG_MSYS= 0
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#
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# Set the path HND_TOP, below, to the 'src'
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# directory checked out from the HND's CVS repository.
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#
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# Below this directory should be the "shared" and "et/sys"
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# directories.
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#
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# The CFE build procedure will pull in sources required
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# for the Ethernet driver from this location.
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#
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HND_TOP=../../../..
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TOP = ../../../cfe
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ARCH = mips
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CPU = bcmcore
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BOARD = bcm4x5x
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include ${TOP}/main/cfe.mk
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#LDLIBS += -lgcc
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ALL : cfe cfe.flash
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echo done
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include ${TOP}/main/cfe_link.mk
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