From 5b5d22fd2725c71eebdfca3f0df8184a824f985a Mon Sep 17 00:00:00 2001
From: Connor McLaughlin <mclaughc@outlook.com>
Date: Fri, 15 Nov 2019 16:44:21 +1000
Subject: [PATCH] SPU: Stub out transfer control register

Fixes sound in Ridge Racer.
---
 src/core/spu.cpp | 16 +++++++++++++++-
 src/core/spu.h   |  8 ++++++++
 2 files changed, 23 insertions(+), 1 deletion(-)

diff --git a/src/core/spu.cpp b/src/core/spu.cpp
index ebe49c8d7..d0cf829fb 100644
--- a/src/core/spu.cpp
+++ b/src/core/spu.cpp
@@ -72,6 +72,7 @@ bool SPU::DoState(StateWrapper& sw)
 {
   sw.Do(&m_SPUCNT.bits);
   sw.Do(&m_SPUSTAT.bits);
+  sw.Do(&m_transfer_control.bits);
   sw.Do(&m_transfer_address);
   sw.Do(&m_transfer_address_reg);
   sw.Do(&m_irq_address);
@@ -172,6 +173,10 @@ u16 SPU::ReadRegister(u32 offset)
       Log_DebugPrintf("SPU control register -> 0x%04X", ZeroExtend32(m_SPUCNT.bits));
       return m_SPUCNT.bits;
 
+    case 0x1F801DAC - SPU_BASE:
+      Log_DebugPrintf("SPU transfer control register -> 0x%04X", ZeroExtend32(m_transfer_control.bits));
+      return m_transfer_control.bits;
+
     case 0x1F801DAE - SPU_BASE:
       // Log_DebugPrintf("SPU status register -> 0x%04X", ZeroExtend32(m_SPUCNT.bits));
       return m_SPUSTAT.bits;
@@ -350,7 +355,7 @@ void SPU::WriteRegister(u32 offset, u16 value)
     {
       Log_DebugPrintf("SPU transfer address register <- 0x%04X", ZeroExtend32(value));
       m_transfer_address_reg = value;
-      m_transfer_address = (ZeroExtend32(value) << VOICE_ADDRESS_SHIFT) & RAM_MASK;
+      m_transfer_address = ZeroExtend32(value) * 8;
       return;
     }
 
@@ -376,6 +381,13 @@ void SPU::WriteRegister(u32 offset, u16 value)
       return;
     }
 
+    case 0x1F801DAC - SPU_BASE:
+    {
+      Log_DebugPrintf("SPU transfer control register <- 0x%04X", ZeroExtend32(value));
+      m_transfer_control.bits = value;
+      return;
+    }
+
     case 0x1F801DB0 - SPU_BASE:
     {
       Log_DebugPrintf("SPU left cd audio register <- 0x%04X", ZeroExtend32(value));
@@ -529,6 +541,7 @@ void SPU::DMAWrite(const u32* words, u32 word_count)
   }
   else
   {
+    DebugAssert(m_transfer_control.mode == 2);
     std::memcpy(&m_ram[m_transfer_address], words, sizeof(u32) * word_count);
     m_transfer_address = (m_transfer_address + (sizeof(u32) * word_count)) & RAM_MASK;
   }
@@ -557,6 +570,7 @@ void SPU::RAMTransferWrite(u16 value)
 {
   Log_TracePrintf("SPU RAM @ 0x%08X (voice 0x%04X) <- 0x%04X", m_transfer_address,
                   m_transfer_address >> VOICE_ADDRESS_SHIFT, ZeroExtend32(value));
+  DebugAssert(m_transfer_control.mode == 2);
 
   std::memcpy(&m_ram[m_transfer_address], &value, sizeof(value));
   m_transfer_address = (m_transfer_address + sizeof(value)) & RAM_MASK;
diff --git a/src/core/spu.h b/src/core/spu.h
index d8e4f96db..21e354002 100644
--- a/src/core/spu.h
+++ b/src/core/spu.h
@@ -95,6 +95,13 @@ private:
     BitField<u16, u8, 0, 6> mode;
   };
 
+  union TransferControl
+  {
+    u16 bits;
+
+    BitField<u8, u8, 1, 3> mode;
+  };
+
   union ADSRRegister
   {
     u32 bits;
@@ -285,6 +292,7 @@ private:
   SPUCNT m_SPUCNT = {};
   SPUSTAT m_SPUSTAT = {};
 
+  TransferControl m_transfer_control = {};
   u16 m_transfer_address_reg = 0;
   u32 m_transfer_address = 0;