mirror of https://github.com/stenzek/duckstation
GTE: Stub and register read/write function
Connor McLaughlin
6 years ago
parent
6df8d42480
commit
4025d6e4a6
@ -1,192 +0,0 @@
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#include "cpu_bus.h"
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#include "YBaseLib/ByteStream.h"
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#include "YBaseLib/Log.h"
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#include "YBaseLib/String.h"
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#include <cstdio>
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Log_SetChannel(Bus);
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Bus::Bus() = default;
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Bus::~Bus() = default;
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bool Bus::Initialize(System* system)
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{
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if (!LoadBIOS())
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return false;
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return true;
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}
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void Bus::Reset()
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{
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m_ram.fill(static_cast<u8>(0));
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}
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bool Bus::DoState(StateWrapper& sw)
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{
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return false;
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}
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bool Bus::ReadByte(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u8* value)
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{
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u32 temp = 0;
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const bool result = DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Byte>(cpu_address, bus_address, temp);
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*value = Truncate8(temp);
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return result;
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}
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bool Bus::ReadWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u16* value)
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{
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u32 temp = 0;
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const bool result =
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DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(cpu_address, bus_address, temp);
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*value = Truncate16(temp);
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return result;
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}
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bool Bus::ReadDWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u32* value)
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{
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return DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Word>(cpu_address, bus_address, *value);
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}
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bool Bus::WriteByte(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u8 value)
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{
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u32 temp = ZeroExtend32(value);
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return DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::Byte>(cpu_address, bus_address, temp);
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}
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bool Bus::WriteWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u16 value)
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{
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u32 temp = ZeroExtend32(value);
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return DispatchAccess<MemoryAccessType::Read, MemoryAccessSize::HalfWord>(cpu_address, bus_address, temp);
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}
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bool Bus::WriteDWord(PhysicalMemoryAddress cpu_address, PhysicalMemoryAddress bus_address, u32 value)
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{
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return DispatchAccess<MemoryAccessType::Write, MemoryAccessSize::Word>(cpu_address, bus_address, value);
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}
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bool Bus::LoadBIOS()
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{
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std::FILE* fp = std::fopen("SCPH1001.BIN", "rb");
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if (!fp)
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return false;
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std::fseek(fp, 0, SEEK_END);
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const u32 size = static_cast<u32>(std::ftell(fp));
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std::fseek(fp, 0, SEEK_SET);
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if (size != m_bios.size())
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{
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Log_ErrorPrintf("BIOS image mismatch, expecting %u bytes, got %u bytes", static_cast<u32>(m_bios.size()), size);
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std::fclose(fp);
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return false;
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}
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if (std::fread(m_bios.data(), 1, m_bios.size(), fp) != m_bios.size())
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{
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Log_ErrorPrintf("Failed to read BIOS image");
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std::fclose(fp);
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return false;
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}
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std::fclose(fp);
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#if 1
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auto Patch = [this](u32 address, u32 value) { std::memcpy(&m_bios[address], &value, sizeof(value)); };
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Patch(0x6F0C, 0x24010001); // addiu $at, $zero, 1
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Patch(0x6F14, 0xaf81a9c0); // sw at, -0x5640(gp)
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#endif
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return true;
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}
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bool Bus::DoInvalidAccess(MemoryAccessType type, MemoryAccessSize size, PhysicalMemoryAddress cpu_address,
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PhysicalMemoryAddress bus_address, u32& value)
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{
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SmallString str;
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str.AppendString("Invalid bus ");
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if (size == MemoryAccessSize::Byte)
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str.AppendString("byte");
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if (size == MemoryAccessSize::HalfWord)
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str.AppendString("word");
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if (size == MemoryAccessSize::Word)
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str.AppendString("dword");
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str.AppendCharacter(' ');
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if (type == MemoryAccessType::Read)
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str.AppendString("read");
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else
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str.AppendString("write");
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str.AppendFormattedString(" at address 0x%08X (virtual address 0x%08X)", bus_address, cpu_address);
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if (type == MemoryAccessType::Write)
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str.AppendFormattedString(" (value 0x%08X)", value);
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Log_ErrorPrint(str);
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if (type == MemoryAccessType::Read)
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value = UINT32_C(0xFFFFFFFF);
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return true;
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}
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bool Bus::ReadExpansionRegion2(MemoryAccessSize size, u32 offset, u32& value)
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{
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offset &= EXP2_MASK;
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// rx/tx buffer empty
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if (offset == 0x21)
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{
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value = 0x04 | 0x08;
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return true;
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}
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return DoInvalidAccess(MemoryAccessType::Read, size, EXP2_BASE | offset, EXP2_BASE | offset, value);
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}
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bool Bus::WriteExpansionRegion2(MemoryAccessSize size, u32 offset, u32 value)
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{
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offset &= EXP2_MASK;
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if (offset == 0x23)
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{
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if (value == '\r')
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return true;
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if (value == '\n')
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{
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if (!m_tty_line_buffer.IsEmpty())
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Log_InfoPrintf("TTY: %s", m_tty_line_buffer.GetCharArray());
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m_tty_line_buffer.Clear();
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}
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else
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{
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m_tty_line_buffer.AppendCharacter(Truncate8(value));
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}
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return true;
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}
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if (offset == 0x41)
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{
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Log_WarningPrintf("BIOS POST status: %02X", value & UINT32_C(0x0F));
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return true;
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}
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return DoInvalidAccess(MemoryAccessType::Write, size, EXP2_BASE | offset, EXP2_BASE | offset, value);
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}
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bool Bus::ReadSPU(MemoryAccessSize size, u32 offset, u32& value)
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{
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if (offset == 0x1AE)
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{
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value = 0;
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return true;
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}
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return DoInvalidAccess(MemoryAccessType::Write, size, SPU_BASE | offset, SPU_BASE | offset, value);
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}
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bool Bus::WriteSPU(MemoryAccessSize size, u32 offset, u32 value)
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{
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return DoInvalidAccess(MemoryAccessType::Write, size, SPU_BASE | offset, SPU_BASE | offset, value);
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}
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@ -0,0 +1,24 @@
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#include "gte.h"
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namespace GTE {
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Core::Core() = default;
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Core::~Core() = default;
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void Core::Initialize() {}
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void Core::Reset()
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{
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m_regs = {};
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}
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bool Core::DoState(StateWrapper& sw)
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{
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sw.DoPOD(&m_regs);
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return !sw.HasError();
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}
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void Core::ExecuteInstruction(Instruction inst) {}
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} // namespace GTE
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@ -0,0 +1,32 @@
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#pragma once
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#include "common/state_wrapper.h"
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#include "gte_types.h"
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namespace GTE {
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class Core
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{
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public:
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Core();
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~Core();
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void Initialize();
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void Reset();
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bool DoState(StateWrapper& sw);
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u32 ReadRegister(u32 index) const { return m_regs.r32[index]; }
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void WriteRegister(u32 index, u32 value) { m_regs.r32[index] = value; }
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u32 ReadDataRegister(u32 index) const { return m_regs.r32[index]; }
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void WriteDataRegister(u32 index, u32 value) { m_regs.r32[index] = value; }
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u32 ReadControlRegister(u32 index) const { return m_regs.r32[index + 32]; }
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void WriteControlRegister(u32 index, u32 value) { m_regs.r32[index + 32] = value; }
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void ExecuteInstruction(Instruction inst);
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private:
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Regs m_regs = {};
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};
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} // namespace GTE
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@ -0,0 +1,103 @@
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#pragma once
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#include "common/bitfield.h"
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#include "types.h"
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namespace GTE {
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static constexpr u32 NUM_REGS = 64;
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union Regs
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{
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u32 r32[NUM_REGS];
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#pragma pack(push, 1)
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struct
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{
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s16 V0[3]; // 0-1
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u16 pad1; // 1
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s16 V1[3]; // 2-3
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u16 pad2; // 3
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s16 V2[3]; // 4-5
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u16 pad3; // 5
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u8 RGBC[4]; // 6
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u16 OTZ; // 7
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u16 pad4; // 7
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s16 IR0; // 8
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u16 pad5; // 8
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s16 IR1; // 9
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u16 pad6; // 9
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s16 IR2; // 10
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u16 pad7; // 10
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s16 IR3; // 11
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u16 pad8; // 11
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s16 SXY0; // 12
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u16 pad9; // 12
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s16 SXY1; // 13
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u16 pad10; // 13
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s16 SXY2; // 14
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u16 pad11; // 14
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s16 SXYP; // 15
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u16 pad12; // 15
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u16 SZ0; // 16
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u16 pad13; // 16
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u16 SZ1; // 17
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u16 pad14; // 17
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u16 SZ2; // 18
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u16 pad15; // 18
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u16 SZ3; // 19
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u16 pad16; // 19
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u32 RGB0; // 20
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u32 RGB1; // 21
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u32 RGB2; // 22
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u32 RES1; // 23
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s32 MAC0; // 24
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s32 MAC1; // 25
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s32 MAC2; // 26
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s32 MAC4; // 27
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u16 IRGB; // 28
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u16 ORGB; // 29
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s32 LZCS; // 30
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s32 LZCR; // 31
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u16 RT[3][3]; // 32-36
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u16 pad17; // 36
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s32 TR[3]; // 37-39
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u16 L[3][3]; // 40-44
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u16 pad18; // 44
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u32 RBK; // 45
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u32 GBK; // 46
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u32 BBK; // 47
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u16 LR[3][3]; // 48-52
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u16 pad19; // 52
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u32 RFC; // 53
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u32 GFC; // 54
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u32 BFC; // 55
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u32 OFX; // 56
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u32 OFY; // 57
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u16 H; // 58
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u16 pad20; // 58
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u16 DQA; // 59
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u16 pad21; // 59
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u32 DQB; // 60
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u16 ZSF3; // 61
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u16 pad22; // 61
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u16 ZSF4; // 62
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u16 pad23; // 62
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u32 FLAG; // 63
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};
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#pragma pack(pop)
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};
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static_assert(sizeof(Regs) == (sizeof(u32) * NUM_REGS));
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union Instruction
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{
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u32 bits;
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BitField<u32, u8, 20, 5> fake_command;
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BitField<u32, u8, 19, 1> sf; // shift fraction in IR registers, 0=no fraction, 1=12bit fraction
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BitField<u32, u8, 17, 2> mvmva_multiply_matrix;
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BitField<u32, u8, 15, 2> mvmva_multiply_vector;
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BitField<u32, u8, 13, 2> mvmva_translation_vector;
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BitField<u32, bool, 10, 1> lm; // saturate IR1, IR2, IR3 result
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BitField<u32, u8, 0, 6> command;
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};
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} // namespace GTE
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