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@ -2476,8 +2476,8 @@ template<PGXPMode pgxp_mode, bool debug>
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if (s_trace_to_log)
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LogInstruction(g_state.current_instruction.bits, g_state.current_instruction_pc, true);
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// handle all mirrors of the syscall trampoline
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const u32 masked_pc = (g_state.current_instruction_pc & PHYSICAL_MEMORY_ADDRESS_MASK);
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// handle all mirrors of the syscall trampoline. will catch 200000A0 etc, but those aren't fetchable anyway
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const u32 masked_pc = (g_state.current_instruction_pc & KSEG_MASK);
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if (masked_pc == 0xA0) [[unlikely]]
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HandleA0Syscall();
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else if (masked_pc == 0xB0) [[unlikely]]
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@ -2721,7 +2721,10 @@ ALWAYS_INLINE_RELEASE bool CPU::DoInstructionRead(PhysicalMemoryAddress address,
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{
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using namespace Bus;
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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// We can shortcut around VirtualAddressToPhysical() here because we're never going to be
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// calling with an out-of-range address.
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DebugAssert(VirtualAddressToPhysical(address) == (address & KSEG_MASK));
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address &= KSEG_MASK;
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if (address < RAM_MIRROR_END)
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{
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@ -2764,7 +2767,8 @@ TickCount CPU::GetInstructionReadTicks(VirtualMemoryAddress address)
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{
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using namespace Bus;
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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DebugAssert(VirtualAddressToPhysical(address) == (address & KSEG_MASK));
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address &= KSEG_MASK;
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if (address < RAM_MIRROR_END)
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{
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@ -2784,7 +2788,8 @@ TickCount CPU::GetICacheFillTicks(VirtualMemoryAddress address)
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{
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using namespace Bus;
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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DebugAssert(VirtualAddressToPhysical(address) == (address & KSEG_MASK));
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address &= KSEG_MASK;
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if (address < RAM_MIRROR_END)
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{
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@ -3030,7 +3035,7 @@ ALWAYS_INLINE bool CPU::DoSafeMemoryAccess(VirtualMemoryAddress address, u32& va
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return true;
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}
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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address &= KSEG_MASK;
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}
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break;
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@ -3046,7 +3051,7 @@ ALWAYS_INLINE bool CPU::DoSafeMemoryAccess(VirtualMemoryAddress address, u32& va
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case 0x05: // KSEG1 - physical memory uncached
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{
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address &= PHYSICAL_MEMORY_ADDRESS_MASK;
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address &= KSEG_MASK;
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}
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break;
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}
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@ -3231,7 +3236,7 @@ bool CPU::SafeReadMemoryBytes(VirtualMemoryAddress addr, void* data, u32 length)
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using namespace Bus;
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const u32 seg = (addr >> 29);
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if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & PHYSICAL_MEMORY_ADDRESS_MASK) >= RAM_MIRROR_END) ||
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if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & KSEG_MASK) >= RAM_MIRROR_END) ||
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(((addr & g_ram_mask) + length) > g_ram_size))
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{
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u8* ptr = static_cast<u8*>(data);
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@ -3255,7 +3260,7 @@ bool CPU::SafeWriteMemoryBytes(VirtualMemoryAddress addr, const void* data, u32
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using namespace Bus;
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const u32 seg = (addr >> 29);
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if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & PHYSICAL_MEMORY_ADDRESS_MASK) >= RAM_MIRROR_END) ||
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if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & KSEG_MASK) >= RAM_MIRROR_END) ||
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(((addr & g_ram_mask) + length) > g_ram_size))
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{
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const u8* ptr = static_cast<const u8*>(data);
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@ -3284,7 +3289,7 @@ bool CPU::SafeZeroMemoryBytes(VirtualMemoryAddress addr, u32 length)
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using namespace Bus;
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const u32 seg = (addr >> 29);
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if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & PHYSICAL_MEMORY_ADDRESS_MASK) >= RAM_MIRROR_END) ||
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if ((seg != 0 && seg != 4 && seg != 5) || (((addr + length) & KSEG_MASK) >= RAM_MIRROR_END) ||
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(((addr & g_ram_mask) + length) > g_ram_size))
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{
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while ((addr & 3u) != 0 && length > 0)
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@ -3328,7 +3333,7 @@ void* CPU::GetDirectReadMemoryPointer(VirtualMemoryAddress address, MemoryAccess
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if (seg != 0 && seg != 4 && seg != 5)
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return nullptr;
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const PhysicalMemoryAddress paddr = address & PHYSICAL_MEMORY_ADDRESS_MASK;
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const PhysicalMemoryAddress paddr = VirtualAddressToPhysical(address);
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if (paddr < RAM_MIRROR_END)
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{
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if (read_ticks)
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@ -3364,7 +3369,7 @@ void* CPU::GetDirectWriteMemoryPointer(VirtualMemoryAddress address, MemoryAcces
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if (seg != 0 && seg != 4 && seg != 5)
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return nullptr;
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const PhysicalMemoryAddress paddr = address & PHYSICAL_MEMORY_ADDRESS_MASK;
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const PhysicalMemoryAddress paddr = address & KSEG_MASK;
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if (paddr < RAM_MIRROR_END)
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return &g_ram[paddr & g_ram_mask];
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